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jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Stratix V IO pins in bank C & D cannot ramp to 3.3V when VCCIO is source with 3.3V

Why is there difference in voltage level in bank 3C/3D IO pins when setting the current strength between 8mA, 12mA versus 16mA? I am expecting 3.3V on the IO pins but only get 1.5V when setting the c...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

I think it may have something with the VCCPD as it is used to power the

I/O pre-drivers.


I checked the Pin Connection Guidelines for Stratix V; however, it is only mentioned on the 3.0V and not 3.3V.


The voltage on VCCPD is dependent on the VCCIO voltage.

When VCCIO is 3.0V, VCCPD must be 3.0V.

When VCCIO is 2.5V or less, VCCPD must be 2.5V