Stratix V Development board with QSFP ports

Hi Paul,

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I have sourced the tcl file "..\hdl\boards\bemicro_sdk\share\scripts\jtag_cmds_sc.tcl" but when I then try to change the LED values with command "led write 0x23" for example, nothing happens. I assume that that tcl commands script is specifically for the bemicro board.

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This Tcl script is expected to be used from within SystemConsole ... is that where you sourced it?

So long as you did not change the PIO address in the Qsys system, this script will work with any board. The board-specific change needed is the pin assignments.

Cheers,

Dave

Yes I have sourced the file from within SystemConsole under TCL console. I have tried to source the jtag_cmds_sc.tcl for the de2 and also bemicro but when then try to change the LEDs , I receive error : "Sorry, no master nodes found

error: can't read "jtag(master)": no such variable" .

I am looking at the System Console interactive session in Figure 13. Must I use these commands? I am just doing what is in Figure 14 , which is sourcing the tcl file and then trying to change LEDs etc.

I also use pin planner to assign the LED ports to actual pins on the cyclone IV. Is this necessary, because I don't see this in the notes? If that is the case , must I assign all the ports there, including tck,tdi,tdo,tms?

Sorry for the bombardment of questions, but we are determined to get it right ))

Cheers,

Paul

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Yes I have sourced the file from within SystemConsole under TCL console. I have tried to source the jtag_cmds_sc.tcl for the de2 and also bemicro but when then try to change the LEDs , I receive error : "Sorry, no master nodes found

error: can't read "jtag(master)": no such variable" .

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Use this as an opportunity to understand what the scripts do :)

1. Make sure your design contains a JTAG-to-Avalon-MM bridge.

If you look in the hierarchy display in Quartus after synthesis, you should see an sld_hub, and then if you expand the Qsys system, you'll see the jtag_master.

2. Read the SystemConsole Tcl script and read the Quartus handbook section that describes the commands.

The "Sorry, no master nodes found" comes from the jtag_open command, i.e., the Tcl commands

    set master_paths 
    if { == 0} {
        puts "Sorry, no master nodes found"
        return
    }

The Quartus command "get_service_paths master" returns a list of JTAG-to-Avalon-MM bridge components in your design. The fact that it does not find any means that you've either forgotten to download the board, or some other issue.

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I am looking at the System Console interactive session in Figure 13. Must I use these commands? I am just doing what is in Figure 14 , which is sourcing the tcl file and then trying to change LEDs etc.

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If you compare Figure 13 to the jtag_cmds_sc.tcl script, you'll see that the Tcl script simply wraps those commands in user-friendly set of procedures, so what you have done is fine. The problem is that your design is not recognized as having a JTAG-to-Avalon-MM master, i.e., the jtag_open procedure called the first time you try to use jtag_read or jtag_write is failing.

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I also use pin planner to assign the LED ports to actual pins on the cyclone IV. Is this necessary, because I don't see this in the notes? If that is the case , must I assign all the ports there, including tck,tdi,tdo,tms?

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Yeah, you're right, this could be stated a little more explicitly. To a long-time user of FPGAs, its "obvious" that pin assignments change between boards, but this is not the case for new users :)

You must assign the clock and LED pins correctly. The JTAG pins are fixed, so don't worry about assigning them.

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Sorry for the bombardment of questions, but we are determined to get it right ))

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No need to apologize. The tools are often annoying. I've already suffered through the pain and frustration, so I don't mind saving others some grief :)

Cheers,

Dave

Hi Dave,

This would be a separate issue. I have posted it in another forum but no reply yet.

I am following the example tutorial "Using the SDRAM on Altera’s DE2 Board with Verilog Designs" using Qsys. I have built the system and loaded it to the FPGA. I am using the DE0-Nano board again.

How exactly can I test the DDR2 controller in this case? I see only an example on how to test the switches and LEDs there.

I would like to be able to write data to the on-board RAM through the controller from the FPGA and read it back etc. Do I have to worry about all the control signals or will the controller take care of that itself? In order to write data to an address in RAM, how would one go about it?

Thanks,

Paul

Hi Paul,

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This would be a separate issue. I have posted it in another forum but no reply yet.

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I guess I didn't see it :)

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I am following the example tutorial "Using the SDRAM on Altera’s DE2 Board with Verilog Designs" using Qsys. I have built the system and loaded it to the FPGA. I am using the DE0-Nano board again.

How exactly can I test the DDR2 controller in this case? I see only an example on how to test the switches and LEDs there.

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The DE0-nano has SDRAM, not DDR2 ... so your question is inconsistent ...

With DDR memory, the controller is quite complicated and requires calibration of the interface timing. This can be performed using the Transceiver Toolkit. I'm sure your Stratix V board uses DDR2, so I can send you a document on how to create a system that includes the logic required to use the Transceiver Toolkit.

The SDRAM memory on the DE0-nano has static timing requirements. So long as the design includes the correct .sdc file, and it passes timing, then you can just use it. You can test it using a pattern generator and checker, and DMA controller to move data back and forth, or you can just create a really basic test, and read/write.

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I would like to be able to write data to the on-board RAM through the controller from the FPGA and read it back etc. Do I have to worry about all the control signals or will the controller take care of that itself? In order to write data to an address in RAM, how would one go about it?

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The controller takes care of the timing.

You should also be able to create a simulation of the system and include a memory model and read/write that fake memory. If you get that working, then you'll feel a lot more confident things work.

I have a favor to ask ... Do you have any QSFP+ cables for your board yet? I would like to see what the eye pattern measurements are like on the Bittware board. If you have a cable, I can write the top-level HDL, and you can run the test. That way you'll get a working design, and I'll get the test results I want to see, and then I can decide whether I should get one of the Bittware boards.

Cheers,

Dave

Hi Dave,

We are still waiting on the QSFP+ cables for the board. They should hopefully get here before the end of the month. As soon as they arrive I will let you know.

The DE0-nano has SDRAM actually, my bad :-) I therefore don't have an example on how to read and write to it. What would be the best way to do this?

Yes the Bittware board has DDR3 RAM. It would be great to receive a document on how to read and write to it also.

Thanks,

Paul

Hi Paul,

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We are still waiting on the QSFP+ cables for the board. They should hopefully get here before the end of the month. As soon as they arrive I will let you know.

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Ok, thanks. I could always FedEx you my cables if I was dying for the data sooner. Can you send me an email (to the email address that is my forum name) with the zip file to the Bittware board installation. I'll install it on my development machine, and that way I can create example designs for the board for you.

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The DE0-nano has SDRAM actually, my bad :-) I therefore don't have an example on how to read and write to it. What would be the best way to do this?

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Using the JTAG-to-Avalon-MM master.

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Yes the Bittware board has DDR3 RAM. It would be great to receive a document on how to read and write to it also.

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Download the example design for the BeMicro-CV that I posted here (post#5)

http://www.alteraforum.com/forum/showthread.php?t=43992

and it has the basic sequence. If you get stuck, and you've sent me the Bittware design files, I'll be able to help you figure it out.

Cheers,

Dave

Hi Dave,

I have sent you an email also.

I have tried that JTAG-to-Avalon master tutorial but it just uses on-chip RAM. If I wish to use the separate SDRAM on the DE0-nano board, do I just add an SDRAM controller in Qsys instead of on-chip RAM?

How would I then make sure that it communicates with the SDRAM on the board. Looking at the DE0-nano user guide , there are many pins connected to the SDRAM so which pins would I need to assign and to where?

Cheers,

Paul

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I have sent you an email also.

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Thanks!

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I have tried that JTAG-to-Avalon master tutorial but it just uses on-chip RAM. If I wish to use the separate SDRAM on the DE0-nano board, do I just add an SDRAM controller in Qsys instead of on-chip RAM?

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The tutorial is written to be board agnostic, so it does not use any external devices. In your case, you would simply *add* an SDRAM controller to the Qsys system, and assign it a base address that does not conflict with the existing memory map.

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How would I then make sure that it communicates with the SDRAM on the board. Looking at the DE0-nano user guide , there are many pins connected to the SDRAM so which pins would I need to assign and to where?

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The attached zip file contains a top-level design and a constraints file that defines all the pins on the DE0-nano.

If you cannot figure out how to add an SDRAM controller to the design, I can take a look, but you should try to figure it out, as it will be a good learning experience. You should also try to figure out how to create a simulation for the system (that will likely be a little trickier though).

Cheers,

Dave

I have added the SDRAM controller to the qsys and assigned all the pins.

The next step tho I have trouble with and that is how to use it. I have tried that example of writing to the RAM from the host computer via the jtag interface but would like to do it differently.

How to read and write to the SDRAM with either VHDL code or a NIOS program? Must I specify the RAM address everytime on the address lines or do I just send data on data lines? How then would I read the data at a specific SDRAM location? I have been trying to find an example of how this is done but no success yet.

Cheers,

Paul