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I have sent you an email also.
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Thanks!
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I have tried that JTAG-to-Avalon master tutorial but it just uses on-chip RAM. If I wish to use the separate SDRAM on the DE0-nano board, do I just add an SDRAM controller in Qsys instead of on-chip RAM?
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The tutorial is written to be board agnostic, so it does not use any external devices. In your case, you would simply *add* an SDRAM controller to the Qsys system, and assign it a base address that does not conflict with the existing memory map.
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How would I then make sure that it communicates with the SDRAM on the board. Looking at the DE0-nano user guide , there are many pins connected to the SDRAM so which pins would I need to assign and to where?
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The attached zip file contains a top-level design and a constraints file that defines all the pins on the DE0-nano.
If you cannot figure out how to add an SDRAM controller to the design, I can take a look, but you should try to figure it out, as it will be a good learning experience. You should also try to figure out how to create a simulation for the system (that will likely be a little trickier though).
Cheers,
Dave
Honored Contributor
