Ok, we have made some real progress on this today. We can successfully ping out and in from uClinux on a system using the Altera Triple Speed Ethernet MAC.
I will outline our hard-won knowledge:
First, in the words of one of my colleagues, the reason this is so difficult is that this nice, versatile setup has us "feature f$%*ked". There are simply too many options. We first tried the igor mac with the Opencores mac driver. Everything was going great until we realized that the PHY comes out of reset in Gigabit mode, which we could not get to work(nor did we care...all we wanted was 10/100) Not knowing yet how to go through the MDIO interface to change this (Simply set bits 3:0 in reg 27 of the Marvell Phy to 1111, and then reset the phy), we decided to try to port the working case posted on this thread by naceradsky to uClinux.
I wanted to try the SLS MAC driver with this, but I have never been able to get a kernel to boot with it so...we used the (ominously EXPERIMENTAL) Tripple (sic) Speed Ethernet driver that is the other option for this under uClinux. Note, this is a pretty cut down driver, and it doesn't support interfaces used by mii-tool and eth-tool(direct MII manipulation). Also, it doesn't support MAC Address modification.
So, we begin our next adventure:
We patterned our system exactly as in naceradsky's example, and were not able to get anywhere. One reason seemed to be too many features:
The ptf file post by naceradsky, specified a GMII MAC with a PCS. What is a PCS? Apparently it is a phy in and of itself, and requires only a "industry standard" 10 bit interface to an external SERDES to work. Since naceradsky's example works, I can only assume that this PHY can do that, though I have no idea how to make it happen. So, it didn't work for us. One way the problems we had manifested themselves, is that we could not actually read or write to the MDIO interface on the Marvell Phy. This is because, according to the TSE MAC spec, the PCS function is placed at position PHY0 in the MAC, meaning that all MDIO reads are immediately returned on the Avalon bus, because they never actually go to MDIO. Unfortunately, all those reads acted like all MDIO registers were 0. :(
But now, an explanation: The TSE MAC can support up to two phys. Talking to one or the other is done by writing to a separate address space on the MAC. The phy ID, *which in the casre of this board is always 0x12!* is assigned to each space, and is used in all subsequent mdio packets.
Since the ATSE driver (the experimental Tripple Speed Ethernet one), always reads/writes to phy space 0, all reads were going to the PCS, which is communicating with an unconfigured internal phy (apparently).
At that point, we mucked with the MAC driver to access the phy through the phy 1 interface(by telling that interface to reference phy id 0x12, and then reading/writing to the proper MAC address range), and were able to talk to the phy. However, we still could not ping through. We observed the MAC TX FIFO using ClearBlue FPGA, and found that we were driving data into the MAC, but that it wasn't being driven through to the PHY over the GMII interface.
So, we decided to simplify, and we went back to SOPC builder and inserted the standard 10/100/1000 MAC (the one without the PCS). This one is kinda funny, in that it actually creates two whole sets of interface ports, one for GMII (8 bit TX data) and one for MII (4 bit TX data). So, which one to connect? Well, in our case, the correct answer is the MII set (4 bit), and leave the GMII dangling to be optimized away. This, in conjunction with code in the MAC driver to set Phy Register 27 bits 3:0 to 1111b, which sets us to 10/100 MII mode, followed by a software reset by hitting bit 15 of the MAC command register (base + 0x8), FINALLY resulted in a working, 100 Mb, full duplex system under linux. WooHoo!
At this point, you are probably saying "What the...", so let me sum up:
- I am using uClinux (not the new one with MMU support, at least not yet)
- I am using a modified version of the "Experimental" Tripple(Sic) Speed ethernet MAC
- I am using the Altera TSE MAC hardware:10/100/1000 Ethernet MAC with 2048 deep FIFOs.
- I have connected the MII interface to the PHY. This is the 4 bit txd interface.
- Both clocks are coming from the phy (both 25MHz), so no extra PLLs.
- I modified the Tripple(sic) speed ethernet mac driver to set the extended status register (MDIO reg 27) on the PHY:bits 3:0 to 1111. And then I reset the phy by writing a 1 to bit 15 of the MAC command register (BASE + 0x8)
I am including 2 files:
The ptf (appended .txt so that this rediculous forum system would allow me to upload the file)
The top-level interface file
I do not have the atse.c and atse.h available at this moment, but I will post them tomorrow. I just wanted to get this all written down before I forgot any details (of which there are just a couple :) )
If you are using this MAC driver, simply drop these files in nios2-linux/linux-2.6/drivers/net, then rebuild.
Have fun!
Honored Contributor
