[STRATIX 10 SX SoC Development Kit] - Connecting both FPGA and HPS DDR4 controllers to their respective physical memory

I have narrowed down the problem to be related to the pin assignment. I am not an expert on that topic but it seems the pins that connect the HPS to its DDR4 memory are set (in the relevant sample project) at 1.8V while the sample project for the FPGA part works only at 1.2V (according to the FPGA EMIF IP). Whenever I connect in my top-level the FPGA DDR4 pins to the Qsys FPGA EMIF, the compiler crashes.

I am sending the stack trace from the crash report as attachement.

@ADelp1
are u able to test FPGA dual rank DDR4(SODIMM) with example design?
if yes, can u share the example design.
We are not able to do it. we are facing some issue.
if anyone can help us, it will be helpful.

We raised our concern. but we didnt get support

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Stratix-10-SoC-Dev-Kit-L-tile-FPGA-DDR4-SODIMM-Example-design/td-p/1201478