Forum Discussion
ADelp1
New Contributor
New Contributor[STRATIX 10 SX SoC Development Kit] - Connecting both FPGA and HPS DDR4 controllers to their respective physical memory
Hello, For the design I am creating on this Stratix 10 devkit, I need to connect both the FPGA's and HPS' Memory. This is the relevant diagram from the documentation showing the 2 DDR4 modules: ...
sstrell
Super Contributor
Super ContributorI don't know of an example design like that, but since you probably have .qsys files from the two designs, you could either just instantiate them in a top-level HDL design file or create a top-level Platform Designer file and have the two designs as sub-system designs.
What difficulty are you having bringing them together?
#iwork4intel
MIT_R_D
Occasional Contributor
Occasional Contributor@ADelp1
are u able to test FPGA dual rank DDR4(SODIMM) with example design?
if yes, can u share the example design.
We are not able to do it. we are facing some issue.
if anyone can help us, it will be helpful.
We raised our concern. but we didnt get support
- MIT_R_D
We took intel support to short out this DDR Access issue.
