[STRATIX 10 SX SoC Development Kit] - Connecting both FPGA and HPS DDR4 controllers to their respective physical memory

@ADelp1
are u able to test FPGA dual rank DDR4(SODIMM) with example design?
if yes, can u share the example design.
We are not able to do it. we are facing some issue.
if anyone can help us, it will be helpful.

We raised our concern. but we didnt get support

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Stratix-10-SoC-Dev-Kit-L-tile-FPGA-DDR4-SODIMM-Example-design/td-p/1201478