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ADelp1's avatar
ADelp1
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5 years ago

[STRATIX 10 SX SoC Development Kit] - Connecting both FPGA and HPS DDR4 controllers to their respective physical memory

Hello, For the design I am creating on this Stratix 10 devkit, I need to connect both the FPGA's and HPS' Memory. This is the relevant diagram from the documentation showing the 2 DDR4 modules: ...
sstrell's avatar
sstrell
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5 years ago

I don't know of an example design like that, but since you probably have .qsys files from the two designs, you could either just instantiate them in a top-level HDL design file or create a top-level Platform Designer file and have the two designs as sub-system designs.

What difficulty are you having bringing them together?

#iwork4intel

ADelp1's avatar
ADelp1
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5 years ago

I have narrowed down the problem to be related to the pin assignment. I am not an expert on that topic but it seems the pins that connect the HPS to its DDR4 memory are set (in the relevant sample project) at 1.8V while the sample project for the FPGA part works only at 1.2V (according to the FPGA EMIF IP). Whenever I connect in my top-level the FPGA DDR4 pins to the Qsys FPGA EMIF, the compiler crashes.

I am sending the stack trace from the crash report as attachement.