New Contributor
Super ContributorI don't know of an example design like that, but since you probably have .qsys files from the two designs, you could either just instantiate them in a top-level HDL design file or create a top-level Platform Designer file and have the two designs as sub-system designs.
What difficulty are you having bringing them together?
#iwork4intel
New ContributorI have narrowed down the problem to be related to the pin assignment. I am not an expert on that topic but it seems the pins that connect the HPS to its DDR4 memory are set (in the relevant sample project) at 1.8V while the sample project for the FPGA part works only at 1.2V (according to the FPGA EMIF IP). Whenever I connect in my top-level the FPGA DDR4 pins to the Qsys FPGA EMIF, the compiler crashes.
I am sending the stack trace from the crash report as attachement.
Occasional Contributor@ADelp1
are u able to test FPGA dual rank DDR4(SODIMM) with example design?
if yes, can u share the example design.
We are not able to do it. we are facing some issue.
if anyone can help us, it will be helpful.
We raised our concern. but we didnt get support
Occasional Contributor
We took intel support to short out this DDR Access issue.
