Hello - I have one of the Stratix 10 GX development kits, the L-tile version. The card is installed in a Dell Precision 5820 chassis, in slot 4, a x16 Gen3 slot. I'm looking for a known-good PCIe design that supports x16 Gen3 mode. The card is in its original configuration. I'm able to program designs into the FPGA via the USB Blaster-II JTAG connection. Since I am running Linux, after programming the design into the FPGA, I do a 'sudo reboot -h now' to effect a warm-boot and a re-enumeration of the PCI bus. Yet after doing this, regardless of the design I have loaded, I don't see the card in the output of lspci and it's card slot, Slot 4 on the Dell system, still shows as 'Available' in the output of 'sudo dmidecode -t 9'. I would expect the board test package bts_pcie.sof would work for this, yet the card does not seem to enumerate even with this design loaded. Best Regards, John Sambrook Common Sense Systems, Inc.

Hi John, the .sof file and .stp file is generated. But I cannot sent it by here due to forum limitation, I try your register email, it fail as well due to file too large. Do you have any cloud server that I can upload to you ? or can you please file an Intel Premium Support (IPS case) for that ? Hoping to hear back from you Regards, Wincent_Intel

Hi, I wish to follow up with you about this case.Do you have any further questions on this matter ?Else I would like to have your permission to close this forum ticket Regards,Wincent_Intel

Hi John,For Stratix 10 GX, if you are looking at tested design, you may refer to link below for golden_top design example. The .sof file is included for test purposes. https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx.htmlIf you are looking for other Stratix 10 design example, you may refer to our FPGA Design Store - IntelLet me know if this is helpful.Regards,Wincent_Intel

Hello Wincent_Intel, Thanks for the quick and helpful reply. When I have access to the board later this morning, what PCIe Vendor ID and Device ID will the board respond with when the golden_top.sof design is properly programmed and I run sudo lspci from a shell prompt on the system? Best Regards, John Sambrook Common Sense Systems, Inc.

Hi Wincent_Intel, I have the production version of the development kit downloaded. The examples/golden_top folder is an empty design. The readme starts off with "The top file here is only for pin assignment reference. The project is just an empty one without any design example in it." I am looking for an already-compiled design that I can load into my development board and to confirm that the board will enumerate in the Dell 5820 chassis in which the board is located. To cut to the chase, I'm looking for an already compiled design (.sof file) that I can program into my board, while it is in-chassis, that will enumerate when the Linux system is warm-booted. Is the factory default design one such design? Should I be able to plug in my stock development board, with no changes to board configuration (DIP switch settings or anything else) and expect it to enumerate when it's in a working x16 Gen3 slot? Best Regards, John Sambrook Common Sense Systems, Inc.

Stratix 10 GX L-Tile Dev Kit and PCIe | Altera Community

20 Replies

Wincent_Altera
Regular Contributor
3 years ago
Hi,

I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket

Regards,
Wincent_Intel
Wincent_Altera
Regular Contributor
3 years ago
Hi John,

For Stratix 10 GX, if you are looking at tested design, you may refer to link below for golden_top design example.
The .sof file is included for test purposes.
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx.html
If you are looking for other Stratix 10 design example, you may refer to our FPGA Design Store - Intel

Let me know if this is helpful.
Regards,
Wincent_Intel
- JSambrook_CSSI_FPGA
  Occasional Contributor
  3 years ago
  Hello Wincent_Intel,
  
  Thanks for the quick and helpful reply.
  
  When I have access to the board later this morning, what PCIe Vendor ID and Device ID will the board respond with when the golden_top.sof design is properly programmed and I run sudo lspci from a shell prompt on the system?
  
  Best Regards,
  
  John Sambrook
  
  Common Sense Systems, Inc.
- JSambrook_CSSI_FPGA
  Occasional Contributor
  3 years ago
  Hi Wincent_Intel,
  
  I have the production version of the development kit downloaded.
  
  The examples/golden_top folder is an empty design. The readme starts off with
  
  "The top file here is only for pin assignment reference. The project is just an empty
  
  one without any design example in it."
  
  I am looking for an already-compiled design that I can load into my development
  
  board and to confirm that the board will enumerate in the Dell 5820 chassis
  
  in which the board is located.
  
  To cut to the chase, I'm looking for an already compiled design (.sof file) that I can
  
  program into my board, while it is in-chassis, that will enumerate when the Linux
  
  system is warm-booted.
  
  Is the factory default design one such design? Should I be able to plug in my
  
  stock development board, with no changes to board configuration (DIP switch
  
  settings or anything else) and expect it to enumerate when it's in a working
  
  x16 Gen3 slot?
  
  Best Regards,
  
  John Sambrook
  
  Common Sense Systems, Inc.
  - Wincent_Altera
    Regular Contributor
    3 years ago
    Hi John,
    
    There is no already compiled design (.sof file) that is available.
    You need to generate it based on the PCIe design example either AVST, AVMM or MCDMA.
    Detail step to generate the .sof file, you may refer to the Stratix 10 AVST user guide, under Section 1.5 , page 9/12
    
    https://www.intel.com/content/www/us/en/docs/programmable/683361/17-0ir2/introduction.html
    
    Let me know if the step is not clear, if you are unable to perform it.
    
    Regards,
    
    Wincent_Intel
Wincent_Altera
Regular Contributor
3 years ago
Hi,

I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket

Regards,
Wincent_Intel
- JSambrook_CSSI_FPGA
  Occasional Contributor
  3 years ago
  Hi Wincent_Intel,
  
  I would like to leave the ticket open for the time being. If you are not the right
  
  person to handle it, please escalate it.
  
  I think it would be Intel's interests, and its customer's interests, for Intel to
  
  provide customers with a known-good and tested design for debugging
  
  PCIe in-host-system enumeration problems.
  
  I would like Intel to provide at least a single already-compiled and
  
  already-tested design that can be used as is to check out PCIe
  
  enumeration problems in host systems.
  
  It could be a simple x1, Gen3 design specifically intended for helping to
  
  overcome PCIe enumeration problems. Would it take one of your experienced
  
  FPGA engineers more than an afternoon to put such a design together?
  
  It could also be compiled with support for Signal TAP, so that customers
  
  that needed to use that to gain insight into enumeration problems would
  
  have additional information to assist in debugging.
  
  Best Regards,
  
  John Sambrook
  
  Common Sense Systems, Inc.
  - Wincent_Altera
    Regular Contributor
    3 years ago
    Hi John,
    
    Can you provide me your device OPN number ?
    I will generate a .sof file on behave and then sent it back to you.
    
    Regards,
    
    Wincent_Intel
Wincent_Altera
Regular Contributor
3 years ago
Hi John,

Is there any update from my previous message?

Regards,
Wincent_Intel
Wincent_Altera
Regular Contributor
3 years ago
Hi,

I wish to follow up with you about this case.
Is there any method that I can provide the .sof file to you as the file is unable to upload in this forum thread.
The .sof file is quite easy to generate by generating an example design, example PCIe Avalon ST.
Run the synthesis/full compilation.
Open the signal Tap, and capture the signal as below to check the LTSSM linkup/enumeration/
Hoping to hear back from you.

Regards,
Wincent_Intel
- JSambrook_CSSI_FPGA
  Occasional Contributor
  3 years ago
  Hi Wincent,
  
  Thanks for your reply. I can send you credentials to store the file on my Dropbox.
  
  Is there are direct email address I can use that will reach you?
  
  I don't to post the credentials in an open forum here.
  
  You can also try my email address at Protonmail if you want: [email protected].
  
  Best Regards,
  
  John Sambrook
  
  Common Sense Systems, Inc.
Wincent_Altera
Regular Contributor
3 years ago
Hi John,

Did you able to run the .sof and .stp file ?

Regards,
Wincent_Intel
JSambrook_CSSI_FPGA
Occasional Contributor
3 years ago
Hi Wincent -

I have not yet tried it out. I just found this video today and I wanted to ask you about it:

Intel Parallel Flash Loader

Did you use this in your design?

Also, with the Board Test System it's possible to give it a .sof file or a .pof file, is that right?

And if so, does the BTS work properly when doing programming in the manner specified

in the Intel YouTube video linked above?

Thanks in advance for your help.

Best,

John
Wincent_Altera
Regular Contributor
3 years ago
Hi John,

The video was from "configuration IP", it is supported by the other specialist.
If you wish to know more about it , I do suggest you to open a new ticket for that.
I believe the specialist will provide a better opinion than me (specific on that part).

Regards,
Wincent_Intel
JSambrook_CSSI_FPGA
Occasional Contributor
3 years ago
Hi Wincent -

Thanks for your help on this.

After some searching I and one of my colleagues found the following resources. I think they are critical for anyone who wants to program boards like the Stratix 10 GX L-tile board that I have.

Posting them here so that perhaps others will benefit from them:

How to perform Avalon®-ST Configuration by using Parallel Flash loader II Intel® FPGA IP Core

Parallel Flash Loader II: How to convert .sof file to .pof file

Please do go ahead and close this call. Thank you for your help.

Best Regards,

John Sambrook

Common Sense Systems, Inc.
- Wincent_Altera
  Regular Contributor
  3 years ago
  Hi John
  
  Glad that you found the answer, thanks for share with me in here.
  
  Hence, This thread will be transitioned to community support.
  
  If you have a new question, feel free to open a new thread to get support from Intel experts.
  
  Otherwise, the community users will continue to help you on this thread. Thank you
  
  If you feel your support experience was less than a 9 or 10,
  
  please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.
  
  Regards,
  
  Wincent_Intel

Forum Discussion

Stratix 10 GX L-Tile Dev Kit and PCIe

20 Replies

Recent Discussions

DK-DEV-AGI027R1BES FPGA recovery

DK-DEV-AGI027RBES missing device selection

in MAX 10 Dev kit

DK-DEV-AGI027RES Install Package

DK-DEV-AGI027RES Install Package