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JSambrook_CSSI_FPGA's avatar
JSambrook_CSSI_FPGA
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Stratix 10 GX L-Tile Dev Kit and PCIe

Hello - I have one of the Stratix 10 GX development kits, the L-tile version. The card is installed in a Dell Precision 5820 chassis, in slot 4, a x16 Gen3 slot. I'm looking for a known-goo...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


  • JSambrook_CSSI_FPGA's avatar
    JSambrook_CSSI_FPGA
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago
    Hi Wincent_Intel,
    I would like to leave the ticket open for the time being. If you are not the right
    person to handle it, please escalate it.
    I think it would be Intel's interests, and its customer's interests, for Intel to
    provide customers with a known-good and tested design for debugging
    PCIe in-host-system enumeration problems.
    I would like Intel to provide at least a single already-compiled and
    already-tested design that can be used as is to check out PCIe
    enumeration problems in host systems.
    It could be a simple x1, Gen3 design specifically intended for helping to
    overcome PCIe enumeration problems. Would it take one of your experienced
    FPGA engineers more than an afternoon to put such a design together?
    It could also be compiled with support for Signal TAP, so that customers
    that needed to use that to gain insight into enumeration problems would
    have additional information to assist in debugging.

    Best Regards,

    John Sambrook

    Common Sense Systems, Inc.

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi John,

      Can you provide me your device OPN number ?
      I will generate a .sof file on behave and then sent it back to you.

      Regards,

      Wincent_Intel

      • JSambrook_CSSI_FPGA's avatar
        JSambrook_CSSI_FPGA
        Icon for Occasional Contributor rankOccasional Contributor
        3 years ago

        Hello Wincent,

        Thank you kindly for your help with this.

        The Ordering Part Number is 1SG280LU2F50E2VG.

        Will you test the design in the same kind of development kit as I have, so

        that what you send me is something I know has been proven to work in

        other development kits of the same kind?

        My development kit is a DK-DEV-1SGX-L-A.

        Will the design you compile include support for JTAG debug via Signal Tap,
        so that the most important signals for assessing enumeration problems are
        visible?
        Thanks again for your help.
        Best Regards,
        John Sambrook
        Common Sense Systems, Inc.