Hi Wincent_Intel,
I would like to leave the ticket open for the time being. If you are not the right
person to handle it, please escalate it.
I think it would be Intel's interests, and its customer's interests, for Intel to
provide customers with a known-good and tested design for debugging
PCIe in-host-system enumeration problems.
I would like Intel to provide at least a single already-compiled and
already-tested design that can be used as is to check out PCIe
enumeration problems in host systems.
It could be a simple x1, Gen3 design specifically intended for helping to
overcome PCIe enumeration problems. Would it take one of your experienced
FPGA engineers more than an afternoon to put such a design together?
It could also be compiled with support for Signal TAP, so that customers
that needed to use that to gain insight into enumeration problems would
have additional information to assist in debugging.
Best Regards,
John Sambrook
Common Sense Systems, Inc.
Occasional Contributor
