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JSambrook_CSSI_FPGA's avatar
JSambrook_CSSI_FPGA
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Stratix 10 GX L-Tile Dev Kit and PCIe

Hello - I have one of the Stratix 10 GX development kits, the L-tile version. The card is installed in a Dell Precision 5820 chassis, in slot 4, a x16 Gen3 slot. I'm looking for a known-goo...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Is there any method that I can provide the .sof file to you as the file is unable to upload in this forum thread.

  1. The .sof file is quite easy to generate by generating an example design, example PCIe Avalon ST.
  2. Run the synthesis/full compilation.
  3. Open the signal Tap, and capture the signal as below to check the LTSSM linkup/enumeration/

Hoping to hear back from you.

Regards,

Wincent_Intel


  • JSambrook_CSSI_FPGA's avatar
    JSambrook_CSSI_FPGA
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Wincent,

    Thanks for your reply. I can send you credentials to store the file on my Dropbox.

    Is there are direct email address I can use that will reach you?

    I don't to post the credentials in an open forum here.

    You can also try my email address at Protonmail if you want: john.sambrook@protonmail.com.

    Best Regards,

    John Sambrook

    Common Sense Systems, Inc.