Honored ContributorHi, I want to specify a clock frequency for my counter(VHDL), to make it adds one every second.To simulate it I can simply generate a required waveform, but to configure it into FPGA I think I need a real clock. The default clock requency is 333.56MHz.How can I specify a low frequency for it? :confused:
Anyone can help me out ot this? Thank you!
Honored ContributorYou could use your 333.56Mhz as input to the FPGA.
This could either be used as is if your FPGA is fast enough or via a PLL to reduce it to a more manageable frequency (Say ~10MHz) This clock could then be used to increment a counter.clock_gen: process(clock)
begin
...
if (clock'event and clock = '1') then
if (count = finalCount) then
count <= 0;
clockEnable <= '1';
else
count <= count + 1;
clockEnable <= '0';
end if;
end if;
end process clock_gen;other_stuff : process(clock)
begin
...
if (clock'event and clock = '1') then
if (clockEnable = '1') then
do stuff
end if;
end if;
end process other_stuff;hi, I still have some problem I cannot figure out.I saw in the compilation report that the actual frequency of clockwas around 330 mhz.But the point is I don't think I have introduced the 330mhz clock into my counter, otherwise it should work. :confused:
Could you give some clue how to use a internal clock in my design?many thanks...Honored ContributorIt sounds like you are looking at the output from the timing analyzer.
This tells you the maximum clock frequency that your design will correctly operate under. You must have specified a clock in your top level component. Can you attach an image of where you have seen this clock mentioned and maybe a copy of your code for the top level? There is no such concept as an internally generated clock in an FPGA. There must be an external clock sourceHonored ContributorThankyou~
I saw the max frequency value in the timing analyzer.And here is my code.Honored ContributorI guess, you don't have just a FPGA soldered on a prototype board? All Altera and third party Development Kits have clock oscillators, e.g. 50 MHz. The also have user manuals discussing the clocking schema.
Honored ContributorSo there is a clock defined and you should be able to see this assigned to a pin on your FPGA.
You can input a lower clock frequency to this pin if you like. I noticed in your code the line wait until (CLOCK'event and CLOCK = '1');
if (CLOCK_50'event and CLOCK_50 = '1')thenHi FvM, Well spotted, I didn't pick up on that. Totally agree with you post an that case :)
Honored ContributorThank you guys~I made a clock devider and now the counter works!
Many thanks for your help
