Forum Discussion
Altera_Forum
Honored Contributor
16 years agoSo there is a clock defined and you should be able to see this assigned to a pin on your FPGA.
You can input a lower clock frequency to this pin if you like. I noticed in your code the line wait until (CLOCK'event and CLOCK = '1');
This is behavioral code for test benches and needs to be replaced for RTL design in the FPGA Something like if (CLOCK_50'event and CLOCK_50 = '1')then Would be better