Specify clock frequency for CycloneII FPGA

You could use your 333.56Mhz as input to the FPGA.

This could either be used as is if your FPGA is fast enough or via a PLL to reduce it to a more manageable frequency (Say ~10MHz)

This clock could then be used to increment a counter.

clock_gen: process(clock)
begin
...
if (clock'event and clock = '1') then
if (count = finalCount) then
count <= 0;
clockEnable <= '1';
else
count <= count + 1;
clockEnable <= '0';
end if;
end if;
end process clock_gen;

This counts to a max value and generates a single clock period strobe (a clock enable) every finalCount clocks (at 333MHz).

The finalCount value could be chosen to give the frequency you require.

Then use the clock enable within your addition process.

other_stuff : process(clock)
begin
...
if (clock'event and clock = '1') then
if (clockEnable = '1') then
do stuff
end if;
end if;
end process other_stuff;

Hope this helps