Routing HPS Peripheral pins through FPGA on Agilex-7 SoC: Validation and Software Consideration

Hi

Thanks for contacting us.

Yes, all the peripherals in the dedicated HPS IO bank could be routed through the FPGA.

You could go to the HPS parameter tab>>Pin Mux and Peripherals >> Advanced >> Advanced FPGA Placement.

On boot up the SDM will be responsible to load the FPGA configuration and does not require the linux to be loaded to load the FPGA configuration.

https://cdrdv2-public.intel.com/790902/ug-ag-config-683673-790902.pdf

Hi,

Thank you for your response. I appreciate the clarification.

We plan to utilize the HPS IO bank pins from Agilex 7 by loaning them to the FPGA fabric, allowing us to control these IO pins within the FPGA fabric. This approach is illustrated in the video at https://www.youtube.com/watch?v=cRwzmsJ1Jkg, with a focus on Cyclone V and Arria V SoCs.

Our primary goal is to establish a connection between the daughter card with the RGMII Ethernet PHY and the HPS IO bank. We aim to loan the pins from the HPS IO banks for use in the FPGA and implement the Triple Speed Ethernet IP core for ethernet communication. Therefore, the objective is to employ the TSE IP core within the FPGA fabric instead of relying on the EMAC in the HPS.

The question is whether the feature of HPS IO loaning, as available in Cyclone V and Arria V SoCs, is also present in Agilex 7.

Hi

Yes it is able to for the Agilex7.

However the interface for selecting the loaner IO is slightly different from the older device.

In the Agilex7 you would need to select them under the advance FPGA placement like I show in my previous reply.

Regards

Jingyang, Teh

Hi Jingyang,

There are 2 different stories:

1- Connect the HPS Peripherals' ports to the FPGA fabric and then connect them to the FPGA pins/pads other than HPS-specific FPGA pins/pads. If I'm not mistaken this is what you explained in your earlier reply. In fact, the "Advanced FPGA Placement" tab provides this feature.

2- Connect the HPS-specific FPGA pins/pads to the FPGA fabric and expose those pins to be used by the FPGA fabric. This is what HPS Loaner I/O in Cyclon V and Arria V does (The YouTube video that I already mentioned).

We are looking for the 2nd feature, not the 1st one. We want to get the HPS-specific FPGA pins/pads and connect them to the "Triple Speed Ethernet" IP core. We don't want to use the EMAC from the HPS to drive those pins, we want to use the TSE IP core in FPGA fabric to drive them. Exactly similar to what is done in the YouTube video that I already mentioned.

Thanks!

Hi

So sorry for the misinterpretation.

The 2nd feature that you mentioned is not available for the Agilex7 and only for the ArriaV and CycloneV product.

Regards

Jingyang, Teh

Hi Jingyang,

Thanks for the clarification.

Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh