Routing HPS Peripheral pins through FPGA on Agilex-7 SoC: Validation and Software Consideration

Hi Jingyang,

There are 2 different stories:

1- Connect the HPS Peripherals' ports to the FPGA fabric and then connect them to the FPGA pins/pads other than HPS-specific FPGA pins/pads. If I'm not mistaken this is what you explained in your earlier reply. In fact, the "Advanced FPGA Placement" tab provides this feature.

2- Connect the HPS-specific FPGA pins/pads to the FPGA fabric and expose those pins to be used by the FPGA fabric. This is what HPS Loaner I/O in Cyclon V and Arria V does (The YouTube video that I already mentioned).

We are looking for the 2nd feature, not the 1st one. We want to get the HPS-specific FPGA pins/pads and connect them to the "Triple Speed Ethernet" IP core. We don't want to use the EMAC from the HPS to drive those pins, we want to use the TSE IP core in FPGA fabric to drive them. Exactly similar to what is done in the YouTube video that I already mentioned.

Thanks!