Routing HPS Peripheral pins through FPGA on Agilex-7 SoC: Validation and Software Consideration

Hi,

Thank you for your response. I appreciate the clarification.

We plan to utilize the HPS IO bank pins from Agilex 7 by loaning them to the FPGA fabric, allowing us to control these IO pins within the FPGA fabric. This approach is illustrated in the video at https://www.youtube.com/watch?v=cRwzmsJ1Jkg, with a focus on Cyclone V and Arria V SoCs.

Our primary goal is to establish a connection between the daughter card with the RGMII Ethernet PHY and the HPS IO bank. We aim to loan the pins from the HPS IO banks for use in the FPGA and implement the Triple Speed Ethernet IP core for ethernet communication. Therefore, the objective is to employ the TSE IP core within the FPGA fabric instead of relying on the EMAC in the HPS.

The question is whether the feature of HPS IO loaning, as available in Cyclone V and Arria V SoCs, is also present in Agilex 7.