Problems uploading flash memory -- part 2

Hi Jake,

Thanks for the solution. I also had another issue with 9.1 not able to generate a POF file for the flash. The error(actually an info message) message that I get with 9.1 is "Size of file(s) in CFI_512MB exceeds memory capacity" and then another message saying it failed to generated POF file. I used the COF file that was provided by Altera. But, with the same COF file I can get it to work with 9.0 SP2. I am using Arria II GX dev board and not Startix IV.

I will try to get the patch that you have mentioned and see if the POF file generation issue is resolved as well.

Kumaran

Hi

We have the same problem as described in original post by Eric Harris - unable to program working design into Stratix IV GX FPGA Development Kit via web portal.

We tried to convert with sof2flash from QuartusII 9.0 SP2 as well as QuartusII 9.1 - it makes no difference.

So the questions except the obvious "what's the easiest way to make things work?" are:

1. Should we check on "compressed bitstream" checkbox on setting/Device&Pins Options/Configuratiob tab or better keep it unchecked?

2. Does Development Kit in question support the "Parallel Flash Loader" described in AN386 or the "FPGA-Based Parallel Flash Loader" described in AN478? Or both? Or neither?

3. If it supports PFL from AN386 then where exactly should we specify the address of the user hardware image in the flash memory (0x2c0000)? Convert programming files dialog doesn't get me to change the address of the sof.

4. If it supports PFL from AN478 then I'd like to get precompiled image of FPGA with PFL. Or, at least the ready-made project that I could easily compile.

Now rant on.

5. Why the user guide so f****ing unusable when it comes to flash programming methods others than BUP?

6. How 9.1 was shipped with such an obvious bug? Nobody in Altera's QA never attempted to burn a user image into the flash with the only method officially recommended in the user guide?

7. Why the problem is not documented in the latest release notes?

8. Why patch 73 is not available for free download on Altera web site?

1. check the MSEL pin. It should not use compressed.

2. It supports both. PFL in MAX2 device is used to load FPGA data out from Flash where as FPGA base PFL will be allow you to write FPGA data into Flash

3. The option bit address is 0x18000, first page of FPGA data should be 0x20000, second page should be 0xC20000. You should be able to change address for each page, it will be written as option bit.

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1. check the MSEL pin. It should not use compressed.

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I don't understand what you are talking about. There is no checkbox called "MSEL pin" on Setting/Device&Pins Options/Configuratiob tab.

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2. It supports both. PFL in MAX2 device is used to load FPGA data out from Flash where as FPGA base PFL will be allow you to write FPGA data into Flash

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According to AN 386:

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The Max II PFL feature has the following functions:

■ Programming the CFI flash device through the MAX II JTAG interface.

■ Controlling Altera FPGA configuration from a CFI flash for ACEX® 1K,

APEX™ 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II,

Arria® series, Cyclone® series, FLEX® 10K (FLEX 10KE and FLEX 10KA),

Mercury™, and Stratix® series FPGA devices.

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It seems to me, default MaxII on Stratix IV GX devkit only capable of the second part - controlling Altera FPGA configuration. At least for me, programming CFI flash with MAX II doesn't work at all.

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3. The option bit address is 0x18000, first page of FPGA data should be 0x20000, second page should be 0xC20000. You should be able to change address for each page, it will be written as option bit.

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You forgot to mention that in order to be capable to modify the address one should change "Address mode for selected pages" from "Auto" to "Start".

Anyway, thanks Altera, I wasted another couple of hours.

Now trying to solve it with PFL from AN478.

MSEL is a FPGA pin which determine if you can use compress mode or not

As I mentioned, the PFL in max2 on this board only supports loading data, and PFL in FPGA on this board only supports write Flash function. It is just a matter of what external chip can do and what already implemented in the max2. If you change max2 PFL, sure you can write into Flash. So AN386 is still correct.

Yes, you need to set start or block, otherwise, auto will set start/end (most likely, start from 0x00 and the next page to be right after the previous page)

O.k. The combination of Stratix-IV-based flash programmer (as in AN 478) with MAX2-based fpga loader (as in AN 386) appears to work.

Still, it took way too much time and effort.

IMHO, somebody from Altera support organization has to write step-by-step description of the process. In particular, for a person that has no intimate knowledge of PFL it is not at all obvious that OPTION bits should not be programmed into the flash.

Also pre-build SOF image containing properly instantiated PFL module should be made available on Altera web site as well as included in distribution package of the dev. kit (preferable in zip form rather than in .exe and/or .qar form, because it should be usable on machine that has no Quartus installed by person that has no administrator/power_user privilege).

If you have Quartus II 9.1 SP1 installed, you no longer need to program the device first and then read it back as .flash file.

To convert a .sof to a .flash file, use the following command in Quartus II 9.1 SP1:

sof2flash --pfl --optionbit=<option bit address offset> --input=<your SOF.sof> --output=<output.flash> --offset=<desired image offset>

For example, to create a .flash file for the Stratix IV GX Development kit

sof2flash --input=<yourfile>.sof --output=<yourfile>.flash --offset=0xC20000 --pfl --optionbit=0x18000

Output:

• A FLASH file containing the SOF data.

• A FLASH file containing single image option bits for the PFL located at the address you specified with the --optionbit=<offset> option.

You should only program the *.map.flash file to flash if either of the following applies:

1. You don't have existing option bits at the appropriate location in flash

2. You only need to configure a single image.

Note that most of the Altera development board should already have the option bits, so there is no need to program the *.map.flash

Thank you, sirene. BUP works now.

Out of curiously, why do we need this new --pfl flag? I was under impression that PFL programming data stream is exactly the same as [uncompressed] passive serial which is supposedly a default for sof2flash. However the fact is - on S4-GX devkit without new flag PFL doesn't work. Where is a catch?

Another question. Why is sof2flash so damn slow?

I already figured out that Altera tools programmer, especially those from the assembler, sopcbuilder and Nios sides, value their time well above their customers time so they code in perl, tcl or at best in java what for the customer's benefit should be coded in C/C++. However in case of 'sof2flash --pfl' the slowness was taken to a new extreme and now, instead of being just annoying, it really disturbs the development process.

Hi MSHATZ,

I don't think I have good answers for you this time, but I think somewhere in the development kit collateral it says that sof2flash in 9.1 does not support Stratix IV GX. I guess in order to support it, they have to create a new --pfl option just to indicate that this is for PFL and there'll possible be multiple sof files in the flash.

Also not sure why the sof2flash is slow, possibly due to the sheer size of the programming file (considering Stratix IV GX is a big device?) I'm not sure though, but if you have some comparison, you should probably report it back to Altera.

Thanks.

FWIW, I am having this same problem using 10.1. This is the command I'm using:

sof2flash --pfl --input=in.sof --output=out.flash --offset=0xC20000 --optionbit=0x18000 --programmingmode=PS

or

sof2flash --pfl --input=in.sof --output=out.flash --offset=0xC20000 --optionbit=0x18000 --programmingmode=FPP

They both fail with this:

java.lang.NullPointerException

at com.altera.utilities.Launcher.read(Launcher.java:307)

at com.altera.utilities.Launcher.read(Launcher.java:362)

at com.altera.sof2flash.PFLFlashGenerator.convertHexToSREC(PFLFlashGenerator.java:239)

at com.altera.sof2flash.PFLFlashGenerator.pflgen(PFLFlashGenerator.java:37)

at com.altera.sof2flash.Sof2flash.<init>(Sof2flash.java:122)

at com.altera.sof2flash.Sof2flash.main(Sof2flash.java:77)

It's amazing to me that they have a devkit that is so difficult (if not impossible) to put your own design on. My experiences with Xilinx have been much better.