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1. check the MSEL pin. It should not use compressed.
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I don't understand what you are talking about. There is no checkbox called "MSEL pin" on Setting/Device&Pins Options/Configuratiob tab.
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2. It supports both. PFL in MAX2 device is used to load FPGA data out from Flash where as FPGA base PFL will be allow you to write FPGA data into Flash
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According to AN 386:
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The Max II PFL feature has the following functions:
■ Programming the CFI flash device through the MAX II JTAG interface.
■ Controlling Altera FPGA configuration from a CFI flash for ACEX® 1K,
APEX™ 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II,
Arria® series, Cyclone® series, FLEX® 10K (FLEX 10KE and FLEX 10KA),
Mercury™, and Stratix® series FPGA devices.
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It seems to me, default MaxII on Stratix IV GX devkit only capable of the second part - controlling Altera FPGA configuration. At least for me, programming CFI flash with MAX II doesn't work at all.
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3. The option bit address is 0x18000, first page of FPGA data should be 0x20000, second page should be 0xC20000. You should be able to change address for each page, it will be written as option bit.
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You forgot to mention that in order to be capable to modify the address one should change "Address mode for selected pages" from "Auto" to "Start".
Anyway, thanks Altera, I wasted another couple of hours.
Now trying to solve it with PFL from AN478.
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