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JensVkb's avatar
JensVkb
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Possible to simulate error behaviour - On Chip Flash IP?

I would like to simulate the error behaviour of my design, that uses the on chip flash IP.

I'm able to simulate the desired behaviour, reprogramming of CFM0 and CFM1, and I would now like to trigger the error behaviour designed into the functionality. I would like to see if my design behaves as desired when the on chip flash IP block reports an error or when data-readback shows a mismatch with the data that should have been programmed.

Is it possible to trigger such errors with the simulation of the on chip flash IP? Or do I have to change my design to incorporate a 'corruptor' block to fake on chip flash IP errors and insert that corruptor between the on chip flash IP block and the component interacting with it?

(this but than I would somehow need to verify that this corruptor block is definitely not present in the actual design)

5 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I checked and the Intel On Chip Flash IP does not have parameters or setting that can be customized to do what you intended. The IP is designed to work as indicated in the UG.

    You might need to customize the IP itself.


    Best Regards,

    Richard Tan



  • JensVkb's avatar
    JensVkb
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    @Farabi Thanks for your answer, but unless I'm mistaken, those links just explain how to set up a simulation. I already know how to do that. I am able to simulate the on-chip flash IP. I am able to simulate the design to see how it behaves under normal conditions.

    I would like to know how to influence the on-chip flash IP block or how to interact with it during simulation, so it would provide error conditions in order to test how my design behaves when it sees those errors. E.g. it would be ideal if I can influence the on-chip flash IP block to report an erase or write error. Or to give wrong data for a read command.

    If this is not possible trough interaction with the IP block, I will have to make a fault injection component and include that in my design, which is not preferred.

  • JensVkb's avatar
    JensVkb
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    @RichardTanSY_Altera makes sense.

    I figured it out: I'm using the modelsim force command to at certain times, force a '0' or corrupt the data. Might not be perfect, but it does mean no change in my design is needed and it gets the job done.

    Not sure how I would change the IP, since those source files are encrypted... but as said: figured out a way to accomplish what I need.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Happy to know that you're able to figure a way.

    Customize the IP might takes effort, with only the top level files customizable e.g. parameters . Might as well use the simpler solution that you have found.


    Since this thread has been resolved, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Best Regards,

    Richard Tan


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.