Forum Discussion

Occasional Contributor

3 years ago

Possible to simulate error behaviour - On Chip Flash IP?

I would like to simulate the error behaviour of my design, that uses the on chip flash IP. I'm able to simulate the desired behaviour, reprogramming of CFM0 and CFM1, and I would now like to trigge...

Farabi

Regular Contributor

3 years ago

Hello,

There is guide on how to simulate the Intel IP Core (including on-chip flash IP) - refer page 4-6.

link :https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/hb/max-10/ug-m10-ufm.pdf

and design example : https://www.intel.com/content/www/us/en/design-example/715151/max-10-utilizing-the-user-flash-memory-ufm-with-a-nios-ii-processor.html

regards,

Farabi

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Possible to simulate error behaviour - On Chip Flash IP?

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