Possible to simulate error behaviour - On Chip Flash IP?

@Farabi Thanks for your answer, but unless I'm mistaken, those links just explain how to set up a simulation. I already know how to do that. I am able to simulate the on-chip flash IP. I am able to simulate the design to see how it behaves under normal conditions.

I would like to know how to influence the on-chip flash IP block or how to interact with it during simulation, so it would provide error conditions in order to test how my design behaves when it sees those errors. E.g. it would be ideal if I can influence the on-chip flash IP block to report an erase or write error. Or to give wrong data for a read command.

If this is not possible trough interaction with the IP block, I will have to make a fault injection component and include that in my design, which is not preferred.