Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks!

Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here...

--- Quote Start --- Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks! --- Quote End --- I suggest you use simple socket server (depending upon your application, you can also convert it to a "simple socket client") example as your apllication requires reception of data only. Can you write what exactly that SSRAM doing in this example? If it is an external RAM, you can always replace it with any other RAM that is available to you.

--- Quote Start --- Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here... --- Quote End --- When you get "Verify failed between address" message, just check the address range in that. You can then find out exactly which component is not working (though this error usually indicates problem with boot_flash).

I would like to start this by thanking for your response,Vizziee. I'm trying to use the PCIe Dev Kit to capture Ethernet packages to process it in the NiosII using 1 GBs' interface, via RJ-45, and in the future using the optical interface. But, to make it in that board I think that I need this basic architecture: NiosII -> DDR2 -> SGDMA -> TSE -> (RJ-45 or SPF) In that board I have those memories: MT47H32M16CC-3 32Mx16 and a MT47H64M8CB-3 32Mx8. In Cyclone II Dev Kit is more simple, because I can use a Cypress SRAM, that is more simple than the these ones. I made what you said and discovered the "Verify failed between address" was in DDR2 memory section. I'm using the an517 tutorial, making the modifications to PCIe Dev Kit, and now I have this problem: --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 2, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused --- Quote End --- PS: I didn't connect the TSE module yet, I'm just trying to configure the DDR2 correctly first. Altera says this abou this erro: http://www.altera.com/support/kdb/solutions/rd07272007_849.html But I realy don't know...

Lerxt, Your first error was received because the NIOS IDE attempted to download your application code to the memory that you specified as your program memory in the system library settings. However, after it tried to download, it attempted to verify that the memory was programmed correctly and failed. This probably occurred because your DDR2 interface is not operating correctly. Could you please post a screenshot of your SOPC builder system? Your second error usually occurs for one of two reasons: 1 - Your clock or reset connection to your processor is stuck. 2 - Your clock or reset connection to your DDR2 interface is stuck. This one is less obvious. I assume you are using a clock crossing bridge between your NIOS processor and the DDR2 memory. If the DDR2 interface clock is stuck, the FIFO within the clock crossing bridge never gets emptied which results in a waitrequest signal being permanently asserted to the NIOS' Avalon master. Then the system hangs. The fix for the second error is to just make sure everything is connected properly, your clocks are running as they should be, and your reset signals aren't stuck active. Jake

PCIe Dev Kit Stratix II GX and the TSE MegaCore

47 Replies

Altera_Forum
Honored Contributor
17 years ago
Sorry about the delay, mrbietola, I used this one which I completed.
Change the name to main.c.
jb_altera, you are right, I tested this project with TSE and http://www.niosforum.com/images/spacer.gif Avalon OpenCores 10/100 Ethernet MAC, without success in both.
And you? Did you have any success to port the Simple Socket Server to PCIe Dev Kit, SIIGX?
main.c.txt6 KB
Altera_Forum
Honored Contributor
17 years ago
hi Lerxt, thank you for the program. I have succesfully constrained the ddr and booted uclinux. Now i have to implement the TSE.. where did you find your hardware setup? is the small mac example?
Altera_Forum
Honored Contributor
17 years ago
Hi Lerxt,

No, I still have not had success porting the Simple Socket Server over.
I am now at the same stage you were. I am able to program the .sof file to the device, but then when I try to download the simple_socket_server.elf file, I get:

Using cable "USB-Blaster [USB-0]", device 2, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused

I will let you know if I get anything.

JB
Altera_Forum
Honored Contributor
17 years ago
Hi Lerxt & jb,

I am still trying the sss too. here is where I am:
"
SGDMA desc memory cleared
INFO : TSE MAC 0 found at address 0x06063000
INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : Applying additional PHY configuration of Marvell 88E1111
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Gigabit = 0, Duplex = Full
OK, x=1, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
IP address of et1 : 192.168.1.234
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)
"

I guess this is already something...but no tx led blinking, and no success in telnet yet. I am trying to play with the timing constraints now.
By the way, I had to change the get_ip_addr function in the 'network_utilities.c' program, as the IP address was not correctly decoded (I was putting 192.168.1.234 and I always got 0.1.1.234. so I hardcoded it for the moment). anyway, it does not seem to change anything ;-)

I let you know if I make any progress.
cheers,
Sophie
Altera_Forum
Honored Contributor
17 years ago
Hi Sophie,

That sounds really good. You have no success with telnet, but can you ping it? Also, can you sniff if any messages are sent from your board to the network when it comes up using WireShark or something? Does it even try to get an IP address using DHCP, or does it default to your hardcoded IP address?

If you could post your project (Quartus, not Nios II project), maybe Lerxt and I could take a look, and play around with that (since neither of us can get our .elf to work properly with our .sof)

JB
Altera_Forum
Honored Contributor
17 years ago
hi,
we are trying to use TSE on uclinux, we are at the same point, we set ip an transit to the board, but the board cannot trasmit. I think the problem is in the PHY, we have to configure some registers, anybody have the marvell 88e1111 datasheet?

for the timing constraints, you should modify the tse_mac_constraints.sdh and .tlc using your clocks names i think. For the .sdc file, i have changed the "get_keepers" with "get_ports" because the compiler ignore them like that:

create_clock -period "125 MHz" -name tx_clk_to_the_tse_mac

become

create_clock -period "125 MHz" -name tx_clk
Altera_Forum
Honored Contributor
17 years ago
hi, i get things working in MII mode (100 Mbit)
i think for the GMII mode you should run .sdc and .tcl file with right ethernet constraints (i found it on alteraforum and adapted to 100 Mbit)

you should add a pll to get 125 MHz to gtx_clock and add 90 degree phase shifting for the tx clock going to TSE mac

and least but not last, assure when you ping the pc from the board, that you have firewall disabled! (i saw tx led blinking but no data arrived to pc)

bye
Altera_Forum
Honored Contributor
17 years ago
Wao!
that's great! congratulations!
I am still stucked (now I have a message I did not get before: "tsemac sw reset bit never cleared" just after "INFO : PHY[0.0] - Gigabit = 0, Duplex = Full") but I will test adding a pll + 90 deg phase.
One thing I do not catch is: why do we need to put 125MHz to the gtx even if we do not use the GMII but only the MII... I though that, in MII, the tx_clk was coming from the PHY at 25MHz, and was multiplied by 4 in the tse_mac megacore... Did I misunderstood it?
thanks,
Sophie
PS: would you mind posting your project? It would be great!
Altera_Forum
Honored Contributor
17 years ago
Hi,
You can find attached the archived quartus file of the simple TSE_mac implementation giving the following messages on the NiosII console:
InterNiche Portable TCP/IP, v3.1

Copyright 1996-2007 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Could not locate flash sector with MAC address.
prepped 1 interface, initializing...
[tse_mac_init]
SGDMA desc memory cleared
INFO : TSE MAC 0 found at address 0x06063000
INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : Applying additional PHY configuration of Marvell 88E1111
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Gigabit = 0, Duplex = Full
OK, x=0, CMD_CONFIG=0x01000000

MAC post-initialization: CMD_CONFIG=0x05000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
IP address of et1 : 192.168.1.234
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)

To get that, I press on the reset button (s4) before running the simple socket server program. However, pinging the board still does not work (even with the firewall disabled) and I am starting to run out of ideas now :-(.
cheers,
sophie
ethernet_core.qar3.7 MB
Altera_Forum
Honored Contributor
17 years ago
hi Sophie,
when you use MII mode you have not to use the Gtx clk (that goes in to the PHY).
You also not need the pll.

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PCIe Dev Kit Stratix II GX and the TSE MegaCore

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