Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks!

Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here...

--- Quote Start --- Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks! --- Quote End --- I suggest you use simple socket server (depending upon your application, you can also convert it to a "simple socket client") example as your apllication requires reception of data only. Can you write what exactly that SSRAM doing in this example? If it is an external RAM, you can always replace it with any other RAM that is available to you.

--- Quote Start --- Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here... --- Quote End --- When you get "Verify failed between address" message, just check the address range in that. You can then find out exactly which component is not working (though this error usually indicates problem with boot_flash).

I would like to start this by thanking for your response,Vizziee. I'm trying to use the PCIe Dev Kit to capture Ethernet packages to process it in the NiosII using 1 GBs' interface, via RJ-45, and in the future using the optical interface. But, to make it in that board I think that I need this basic architecture: NiosII -> DDR2 -> SGDMA -> TSE -> (RJ-45 or SPF) In that board I have those memories: MT47H32M16CC-3 32Mx16 and a MT47H64M8CB-3 32Mx8. In Cyclone II Dev Kit is more simple, because I can use a Cypress SRAM, that is more simple than the these ones. I made what you said and discovered the "Verify failed between address" was in DDR2 memory section. I'm using the an517 tutorial, making the modifications to PCIe Dev Kit, and now I have this problem: --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 2, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused --- Quote End --- PS: I didn't connect the TSE module yet, I'm just trying to configure the DDR2 correctly first. Altera says this abou this erro: http://www.altera.com/support/kdb/solutions/rd07272007_849.html But I realy don't know...

Lerxt, Your first error was received because the NIOS IDE attempted to download your application code to the memory that you specified as your program memory in the system library settings. However, after it tried to download, it attempted to verify that the memory was programmed correctly and failed. This probably occurred because your DDR2 interface is not operating correctly. Could you please post a screenshot of your SOPC builder system? Your second error usually occurs for one of two reasons: 1 - Your clock or reset connection to your processor is stuck. 2 - Your clock or reset connection to your DDR2 interface is stuck. This one is less obvious. I assume you are using a clock crossing bridge between your NIOS processor and the DDR2 memory. If the DDR2 interface clock is stuck, the FIFO within the clock crossing bridge never gets emptied which results in a waitrequest signal being permanently asserted to the NIOS' Avalon master. Then the system hangs. The fix for the second error is to just make sure everything is connected properly, your clocks are running as they should be, and your reset signals aren't stuck active. Jake

PCIe Dev Kit Stratix II GX and the TSE MegaCore

47 Replies

Altera_Forum
Honored Contributor
17 years ago
well, happy that you have the same understanding...any progress on your side?
Altera_Forum
Honored Contributor
17 years ago
I have got the same thing, Sophie and mrbietola...

"Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)"

The RX led has blinked, but TX hasn't.
Other problem in this board is the Spansion S29GL512N Memory. Altera don't provide the the file to use correctly this memory.
I know TSE Megacore stores the MAC andress there (Stratix II GX PCI Express Development Board Reference Manual, page 2-16). Because that I set the a static IP to Simple Socket Server.
I have worked in a 1c20 with uClinux for while.
I am going to port uClinux to PCIe Dev Kit and I going to try to run ftp there. If it works, I will post the image and ptf files here.
Altera_Forum
Honored Contributor
17 years ago
hi Lerxt,i have ported uclinux on stratix II GX, for the TSE i utilized the Tripple speed Ethernet Driver (experimental) because the other driver (by SLS) don't work for me (i get kernel panic) i'm configuring the flash now to boot uclinux from it.
To configure flash, i have founded an interesting example on the nioswiki, the example is called "udp offload packet" and it use the same board we have.
http://www.nioswiki.com/exampledesigns/nios2udpoffloadexample

we would do an application on uclinux that brings data from ddr and trasmits over ethernet possibly in Gbit mode (GMII or SGMII interface). In uclinux i think is only supported MII interface (10/100 Mbit/s).
Do you have any experience doing ethernet application on uclinux?
Altera_Forum
Honored Contributor
17 years ago
How did you downloaded the uClinux in PCIe Dev Kit, SIIGX?
I have got this error:

--- Quote Start ---
Can't configure device. Expected JTAG ID code 0x020E30DD for device 1, but found JTAG ID code 0x020A20DD.
--- Quote End ---
That error occurs when I try to use Sophie's sof.
When I use mine, I can download the uClinux as well.
I don't know if this problem is because time
I'm working in a application with pcap lib. I had problem when I tried to compile this lib in uClinux-dist, but, with a friend help, I fixed it.
I had ported this application to uClinux in a 1C20:
http://www.tcpdump.org/sniffex.c
If you post your design, I can create a image of uClinux with this application.
We can do this application, mrbietola... I will try to write a file in DDR and send to a outside database...
Altera_Forum
Honored Contributor
17 years ago
Sorry, Sophie's design is working...
You have to download the sof with Quartus, after that download the uClinux image with Nios Shell.
I don't know how to download the sof with Nios Shell without errors...
Am I right, mrbietola?
Tomorrow, I'll try to generate the uClinux image with TSE driver from Sophie's sof and mine, then I will post them.
Altera_Forum
Honored Contributor
17 years ago
the problem you get in nios shell is common. you have to select the correct device. For USB Blaster i use these commands

nios2-configure-sof -d 2 ddr_time_limited.sof

the option "-d 2 "select the usb blaster
if you use the triple speed ethernet, you have to use the time limited sof

after configure sof:

nios2-download -g -d 2 zImage

nios2-terminal

now should work
Altera_Forum
Honored Contributor
17 years ago
Hi Lerxt and mrbietola,

as promised, I post here a few tricks that I kindly received from Altera FAEs to ease the use of TSE_MAC on Quartus 8.0. You can find:
how to improve the speed of the TSE on Q8.0 (probably useful for mrbietola). file: TSE_80_bugfix
how to solve the problem of the wrong IP address in the network_utilities.c file of the sss (still on 8.0 sp1 version). file: test_simple_socket....On my side I still use the inelegant hardcoded IP address in network_utilities.c file...

http://www.altera.com/support/kdb/solutions/rd01132009_561.html

Finally, a last trick sent to manage to run the signaltap with limited tse_mac core:
"To activate signalatp with quartus webedition see under:
http://www.altera.com/literature/po/ss_quartussevswe.pdf
signaltap II available with talk back feature enabled

You can enable or disable the TalkBack feature in the Quartus® II GUI using the following method:
1. On the Tools menu, select options.
2. In the Options window, select internet connectivity.
3. In the Internet Connectivity dialog window, click the talkback options button.
4. In the TalkBack Options window, enable the turn on the quartus ii software talkback feature option. "

Thanks to the Altera FAEs I was in contact with. Hope this will be useful to you guys,
cheers,
Sophie
multiple-attachments.zip13 KB
Altera_Forum
Honored Contributor
17 years ago
oops, something jumped out from my last reply:

to solve the IP address problem on Quartus 8.1, look at the following links:
http://www.altera.com/support/kdb/kdb-recent.jsp
http://www.altera.com/support/kdb/solutions/rd01132009_561.html

cheers
Altera_Forum
Honored Contributor
17 years ago
Hi all,
i'm usign a Cyclone III Development Board and i'm trying to use simple socket server with TSE megacore.
Here is my console output:

-------------------------------------------------------------------------
InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Could not locate flash sector with MAC address.
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x10022000
INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x01000000

MAC post-initialization: CMD_CONFIG=0x05000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 10.13.13.20
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)

-------------------------------------------------------------------------

I've followed the steps posted before to solve the ip address problem and to improve speed but the RX led blinks and TX doesn't and i can't ping my board.
Any idea about this?
Thank you!
Altera_Forum
Honored Contributor
17 years ago
Hi rvit,
did you reset the phy core before running your sss? for me it is mandatory to get the board answering to a ping.

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PCIe Dev Kit Stratix II GX and the TSE MegaCore

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