New ContributorParallel sum frequency
Hi everyone!
I don't know am I asking question at right place, I need help with optimizing my FPGA project in terms of freqs. I am trying to generate chaotic signal on FPGA board, chaotic oscillator described as IIR filter with nonlinear module (fig. 1), to realize that I used parallel add module from basic functions catalog. I found information about parallel add module only for Stratix devices (fig.2) On my Cyclone® V SE 5CSEMA4U23C6N device I get about 150 MHz FMax (fig. 3) and without non linear module about 200 MHz, am I doing something wrong or Cyclone V is slower than old Stratix devices? Can you give me advice how can I get higher FMax for this project?
And sorry for my poor English.
Sorry for the late reply as I was in vacation,
1. It really depends on how fast you want to run on the particular path. Let say your register to register is running at 200Mhz, and you want that path to run faster, then set max delay is a option to do that. If you want to stick with 200Mhz, just let the Quartus do the job and see if the timing closed? If it is not close, you can try overconstrain or add more pipeline towards the path.
2. Yes, you are right. But if you are using older devices, most likely you will not need this as is for S10 and above hyperflex timing closure. Older device we just monitor the max fan out.
3. It is compulsory to meet both of the model, whether it is fast or slow. You may take a look in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01139-timing-model.pdf, and https://www.youtube.com/watch?v=6D-w8mOttnE at time 26:33
