Forum Discussion
New ContributorParallel sum frequency
Sorry for the late reply as I was in vacation,
1. It really depends on how fast you want to run on the particular path. Let say your register to register is running at 200Mhz, and you want that path to run faster, then set max delay is a option to do that. If you want to stick with 200Mhz, just let the Quartus do the job and see if the timing closed? If it is not close, you can try overconstrain or add more pipeline towards the path.
2. Yes, you are right. But if you are using older devices, most likely you will not need this as is for S10 and above hyperflex timing closure. Older device we just monitor the max fan out.
3. It is compulsory to meet both of the model, whether it is fast or slow. You may take a look in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01139-timing-model.pdf, and https://www.youtube.com/watch?v=6D-w8mOttnE at time 26:33
Super ContributorSorry for the late reply as I was in vacation,
1. It really depends on how fast you want to run on the particular path. Let say your register to register is running at 200Mhz, and you want that path to run faster, then set max delay is a option to do that. If you want to stick with 200Mhz, just let the Quartus do the job and see if the timing closed? If it is not close, you can try overconstrain or add more pipeline towards the path.
2. Yes, you are right. But if you are using older devices, most likely you will not need this as is for S10 and above hyperflex timing closure. Older device we just monitor the max fan out.
3. It is compulsory to meet both of the model, whether it is fast or slow. You may take a look in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01139-timing-model.pdf, and https://www.youtube.com/watch?v=6D-w8mOttnE at time 26:33
New ContributorThank you for reply!
3. Timing analysis shows huge difference between fast and slow models. Whereas fast model reaches up to 330 MHz FMax, slow model reaches only about 200 MHz for same Cyclone V 5CSEMA4U23C6N chip. Therefore, I was wandering how could I provide the chip with required conditions to gain fast model frequencies.
