Forum Discussion
New ContributorParallel sum frequency
Sorry for the late reply as I was in vacation,
1. It really depends on how fast you want to run on the particular path. Let say your register to register is running at 200Mhz, and you want that path to run faster, then set max delay is a option to do that. If you want to stick with 200Mhz, just let the Quartus do the job and see if the timing closed? If it is not close, you can try overconstrain or add more pipeline towards the path.
2. Yes, you are right. But if you are using older devices, most likely you will not need this as is for S10 and above hyperflex timing closure. Older device we just monitor the max fan out.
3. It is compulsory to meet both of the model, whether it is fast or slow. You may take a look in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01139-timing-model.pdf, and https://www.youtube.com/watch?v=6D-w8mOttnE at time 26:33
New ContributorCan time constraints change freqs from 200 MHz up to 470 MHz like for Stratix devices?
Super ContributorAbsolutely. You should have a .sdc file for every design, especially if you're trying to achieve those types of speeds.
- petrosyanmanv
Thank You for your response! I will try to understand the timing analyzer.
- petrosyanmanv
Dear sstrell
On your advice, I began to study timing analysis and I had several questions.
1. Do I understand correctly that setting the minimum and maximum delay constraints is necessary only for asynchronous combinatorial logic? Whether it is necessary to set, apart from the clocks constraints, the delay constraints for the synchronous register-comb logic-register case (fig 1), like set_max_delay -from [get_registers {x_1_3*}] -to [get_registers x_2_1d*] X ns?
2. Also, while reading the literature (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf, page 44), I learned that a large number of outputs from one register can also limit the maximum frequency of the circuit. But I did not find the Design metrics in the timing analyzer in Quartus Light to automatically fix this problem, do I need to purchase the pro version for this?
3. Another question concerns fast and slow models in Quartus. If the time constraints are met for the fast model, but not for the slow model (fig 2), what should I do to make the crystal work in the fast mode?
