Forum Discussion
New ContributorParallel sum frequency
Sorry for the late reply as I was in vacation,
1. It really depends on how fast you want to run on the particular path. Let say your register to register is running at 200Mhz, and you want that path to run faster, then set max delay is a option to do that. If you want to stick with 200Mhz, just let the Quartus do the job and see if the timing closed? If it is not close, you can try overconstrain or add more pipeline towards the path.
2. Yes, you are right. But if you are using older devices, most likely you will not need this as is for S10 and above hyperflex timing closure. Older device we just monitor the max fan out.
3. It is compulsory to meet both of the model, whether it is fast or slow. You may take a look in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01139-timing-model.pdf, and https://www.youtube.com/watch?v=6D-w8mOttnE at time 26:33
Super ContributorWhat does your .sdc file look like?
petrosyanmanvI hoped that project is small and Quartus will anyway compile it fastest possible way, so I didn't make time constraints, do I need to do it?
- petrosyanmanv
Can time constraints change freqs from 200 MHz up to 470 MHz like for Stratix devices?
- sstrell
Absolutely. You should have a .sdc file for every design, especially if you're trying to achieve those types of speeds.
- petrosyanmanv
Thank You for your response! I will try to understand the timing analyzer.
