JTAG chain is broken when DDR4 is enable

Hi,

Do you enable the JTAG debug for the DDR4 IP? Could you check your full design to see what IP does have the JTAG debug features enabled?​

Hi,

1, Yes, I do enable the JTAG debug for the DDR4 IP. (See above image for reference).

Another IP in the design which enable JTAG debug feature is NIOS processor. (see attached image for reference.)

2, The following are JTAG log messages:

$ jtagconfig -d

1) Arria10 IDK [USB-1]

(JTAG Server Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition)

Unable to read device chain - Hardware not attached

Captured DR after reset = (02E660DD)

Captured IR after reset = ()

Captured Bypass after reset = (0)

Captured Bypass chain = ()

JTAG clock speed 6 MHz

$ jtagconfig --getparam 1 JtagClock

6M

$ jtagconfig --setparam 1 JtagClock 24M

No parameter named JtagClock

HI,

Could you check on your board to see if the DDR4 connection is interfering with your JTAG Chain connection? I suspect that there is some signal integrity on your JTAG Chain connection.

Could you try to disable the DDR4 IP's JTAG debugger? I don't think it will be any difference.

I have disabled the DDR4 IP's JTAG debugger as the attached picture, The JTAG chain is still broken:

$ jtagconfig -d

1) Arria10 IDK [USB-1]

(JTAG Server Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition)

Unable to read device chain - Hardware not attached

Captured DR after reset = (02E660DD)

Captured IR after reset = ()

Captured Bypass after reset = (0)

Captured Bypass chain = ()

JTAG clock speed 6 MHz

Hi,

I suspect that either the DDR4 board interface or other IP that is physically crosstalk with the JTAG chain on your board which is causing the issue. I would recommend you to contact​ Reflexces company to check if the board have some issue or not.

HI,

1) I have contacted the Reflexces for Board issues and waiting for their update.

2) At the same time, I have another question about Quartus prime's report for this DDR4 project:

In PLL Usage summary report:

Only five PLLs are listed:

i_pll_sys|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst

eusb31dc_qsys|emif_0|emif_0|arch|arch_inst|pll_inst|pll_inst

eusb31dc_qsys|emif_0|emif_0|arch|arch_inst|pll_inst|pll_inst~_Duplicate

eusb31dc_qsys|emif_0|emif_0|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1

eusb31dc_qsys|emif_0|emif_0|arch|arch_inst|pll_inst|pll_inst~_Duplicate_3

But in Fitter summary report, It reported there are 53 PLLs in the system:

Total RAM Blocks 161 / 2,713 ( 6 % )

Total DSP Blocks 2 / 1,518 ( < 1 % )

Total HSSI RX channels 0 / 48 ( 0 % )

Total HSSI TX channels 0 / 48 ( 0 % )

Total PLLs 53 / 112 ( 47 % )

Why did fitter summary report 53 PLLs in total instead of 5 PLLs?

Moreover, If I remove the DDR4 module from Qsys, Then the fitter summary will report only 1 PLL in total as we expect.

Any idea for the above issue ?

My software version is: Quartus Prime version 18.0 Build 222

09/21/2018 SJ Pro Edition

Hi:

The DDR4 JTAG chain broken issue in Attila dev kit has been fixed with Reflexces company latest MAX 5 FPGA file (MV_Final.pof). Many thanks for your great help!