JTAG chain is broken when DDR4 is enable

Hi,

1, Yes, I do enable the JTAG debug for the DDR4 IP. (See above image for reference).

Another IP in the design which enable JTAG debug feature is NIOS processor. (see attached image for reference.)

2, The following are JTAG log messages:

$ jtagconfig -d

1) Arria10 IDK [USB-1]

(JTAG Server Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition)

Unable to read device chain - Hardware not attached

Captured DR after reset = (02E660DD)

Captured IR after reset = ()

Captured Bypass after reset = (0)

Captured Bypass chain = ()

JTAG clock speed 6 MHz

$ jtagconfig --getparam 1 JtagClock

6M

$ jtagconfig --setparam 1 JtagClock 24M

No parameter named JtagClock