How to point Platform designer generated IPs in Questa Simulation

Hello,

I am trying to simulate a RTL design which contains a modular scatter gather DMA(stream to memory-map) IP generated by Quartus Prime Pro platform designer.

- I am able to generate HDL from the platform designer and instantiate it in my test bench.
- I am able to generate Simulator setup Script for IP (for Questa simulator) using GUI without any error / warnings.

While trying to simulate the design (using Quartus Tools -> Run Simulation -> RTL Simulation option), Simulation is running without error. I can see module instances inside the Questa simulator (QuestaIntel FPGA Edition Edition-64 2024.1). But unable to see any interface signals to/from the platform designer generated IPs in the waveform. I can see all the test bench signals and their transitions in the waveform.

Can anybody suggest where I am going wrong or modifications required (if any) to "run_msim_rtl_verilog.do" file ?

Regards,
Ashish.