Forum Discussion
New ContributorHow to point Platform designer generated IPs in Questa Simulation
Hello,
I am trying to simulate a RTL design which contains a modular scatter gather DMA(stream to memory-map) IP generated by Quartus Prime Pro platform designer.
- I am able to generate HDL from the platform designer and instantiate it in my test bench.
- I am able to generate Simulator setup Script for IP (for Questa simulator) using GUI without any error / warnings.
While trying to simulate the design (using Quartus Tools -> Run Simulation -> RTL Simulation option), Simulation is running without error. I can see module instances inside the Questa simulator (QuestaIntel FPGA Edition Edition-64 2024.1). But unable to see any interface signals to/from the platform designer generated IPs in the waveform. I can see all the test bench signals and their transitions in the waveform.
Can anybody suggest where I am going wrong or modifications required (if any) to "run_msim_rtl_verilog.do" file ?
Regards,
Ashish.
4 Replies
KennyT_alteraSuper Contributor
Can you run through this example https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html
This example show the steps by steps to run the simulation. But for the testbench, i think you will need to create yourself.
- KennyT_altera
Is there any update base on the suggestion above?
Ashish_PradhanHello Kenny_Tan,
Thanks for the suggestions. I am able to simulate it.
Thanks & Regards,
Ashish.
- KennyT_altera
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
