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Ashish_Pradhan's avatar
Ashish_Pradhan
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7 months ago

How to point Platform designer generated IPs in Questa Simulation

Hello, I am trying to simulate a RTL design which contains a modular scatter gather DMA(stream to memory-map) IP generated by Quartus Prime Pro platform designer. - I am able to generate HDL from t...
Board Debug
Fpga Devkit
KennyT_altera's avatar
KennyT_altera
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7 months ago

Is there any update base on the suggestion above?


  • Ashish_Pradhan's avatar
    Ashish_Pradhan
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    7 months ago

    Hello Kenny_Tan,

    Thanks for the suggestions. I am able to simulate it.

    Thanks & Regards,

    Ashish.