Forum Discussion
Ashish_Pradhan
New Contributor
New ContributorHow to point Platform designer generated IPs in Questa Simulation
Hello, I am trying to simulate a RTL design which contains a modular scatter gather DMA(stream to memory-map) IP generated by Quartus Prime Pro platform designer. - I am able to generate HDL from t...
KennyT_altera
Super Contributor
Super ContributorCan you run through this example https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html
This example show the steps by steps to run the simulation. But for the testbench, i think you will need to create yourself.
