Forum Discussion
ContributorExample design: Agilex I-series devkit not detected by lspci (stuck in S_CFG_LINKWD_START)
I've been trying to compile a PCI Express example design for the Agilex I-series devkit.
1. Nothing works on the projects provided here ES (21.2 or higher)
Found here: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/i-series.html
Programming the sof present in the zip using Quartus Pro 21.2, rebooting the server, board not detected by lspci
pcie_ed_inst0|dut|p0_ltssm_state_delay_o[5..0] seems to be stuck to 0x07=S_CFG_LINKWD_START
The motherboard has no issues with any other PCIe cards.
2. Using Quartus Pro 22.1, I followed UG-20330 to generate from scratch the example design.
The compilation ends successfully but the board isn't detected either.
Could you please provide a working example design for the intel devkit already compiled to be sure the problem isn't on the project?
Also what is S_CFG_LINKWD_START?
Regards,
I found the issue.
The default position for the SW3 is defined in the UG as OFF/ON/ON/OFF, to use the refclk from the connector.
The board was received with OFF/OFF/OFF/OFF, to use the on-board refclk.
I set the SW3 as documented and it's now enumerated by the bios and seen in lspci.
Why it doesn't work using the on-board refclks?
Devkit: DK-DEV-AGI027RES
Serial number: AGIPCIE8000248
Regards,
16 Replies
Wincent_AlteraRegular Contributor
Hi,
Can you try the file at the attachment.
also, I suggest trying another Motherboard which is Gen4x16 capable.
Let me know if the problem fixes.Regards,
Wincent_C_Intel
alexislmsHi @Wincent_Altera,
Thank you, it's currently compiling with Quartus Pro 21.2.
At this moment, I don't have a Gen4x16 capable motherboard available, only Gen3x16.
Regards,
- Wincent_Altera
Hi,
I receive a new update on R-tile bug issue, it might be one of the root causes of your problem.
Please refer the link below, download and install the patch, the problem shall fixed in future release
https://www.intel.com/content/www/us/en/support/programmable/articles/000090874.html
Let me know if this help, Looking forward to hear back from you
Regards,
Wincent_C_Intel
- alexislms
Hi @Wincent_Altera,
- I added the smartVID to your project and it programs successfully now.
- I tried 3 different motherboards (up to Gen3x16) and no one detects the card with the 22.1 project and your project.
- I checked several times the physical connection, no issues, it's fully in and it works with all the other PCIe cards we have. Nevertheless, I could only test in lab servers where the card is vertically plugged in due to the PCIe bracket being 1cm taller than the standard size.
Thank you for the patch, I installed it and the project is compiling.
Regards,
- alexislms
I found the issue.
The default position for the SW3 is defined in the UG as OFF/ON/ON/OFF, to use the refclk from the connector.
The board was received with OFF/OFF/OFF/OFF, to use the on-board refclk.
I set the SW3 as documented and it's now enumerated by the bios and seen in lspci.
Why it doesn't work using the on-board refclks?
Devkit: DK-DEV-AGI027RES
Serial number: AGIPCIE8000248
Regards,
- Wincent_Altera
Hi,
Glad that you solve the issue, thanks for sharing with me as well
Seen that the problem happens on the refclks settings if follow Error Code 18948
https://www.intel.com/content/www/us/en/support/programmable/articles/000086828.html
With that, I am setting this case to close status at this time.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
I would appreciate taking a moment to fill out the short survey with regards to your experience using Intel Forum.
Regards,
Wincent_C_Intel
- Wincent_Altera
Hi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with the findings.
Thank you for your patience.
Best regards,
Wincent_C_Intel
- alexislms
Hi @Wincent_Altera,
Thank you for your help, we are completely blocked due to this issue and have no way to debug it by ourselves.
Please let me know if you need anything more.
Best regards,
- Wincent_Altera
Hi,
Initially, I suspend R-Tile's different behavior on different Motherboard may be related to Preset negotiation between Motherboard and R-Tile.
Is okay, let see the result after you compile the file.
Looking forward to hear back from you.
Regards,
Wincent_C_Intel
- alexislms
It compiled successfully but the Programmer fails at 5%:
Error(18950): Device has stopped receiving configuration data Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00040008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Intel Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Error(209012): Operation failedJust in case, I attached the archive of the example design (2. in my question) generated with 22.1.
Regards,
- Wincent_Altera
Hi,
The example work fine in our server, in this case error might happen on the settings.
- Can you please, remove the card from the PCIe slot. Make sure the PCIe edge connector and the slot are clean. Try re-inserting and ensure the card is fully seated in the PCIe slot.
- Have you rebooted Linux after loading the .sof?
- For the Error (22248): Can you please check if the VID setting is appropriate ?
You may refer the guide : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-pwr.pdf#pag... - If not workable, Can you please try out other Agilex Design Example and see is it the error still the same ?
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?s=Newest&f:guidetm83741EA404664A899395C861EDA3D38B=%5BIntel%C2%AE%20Agilex%E2%84%A2%20FPGAs%20and%20SoC%20FPGAs%5D
Looking forward to hear back from you. Please let me know if any other further clarification is needed.
Regards,
Wincent_C_Intel
