Different behavior on different CPLDs

I am using the MAX V series CPLDs, I am experiencing different behavior of same RTL on the different models of MAX V CPLDs,

My RTL works fine on "5M570ZF256C5" but when I port the same onto "5M570ZT100A5N" the behavior gets changed completely.

I have attached the State Machine where I am facing the issue

	CONFIGURE_ADC : process(clk) is
		TYPE StateMachine IS(Init,D1,T1,B1,D2,T2,B2,D3,T3,B3,D4,T4,B4,Stop,Delay,Restart); --state machine data type
		VARIABLE SPIState : StateMachine := Init;  --State machine variable
		variable fifo_memory : fifo_memory_type := (X"00",X"03");
		variable read_memory : read_data_type := (X"00", X"00", X"00", X"00");
		variable fifo_head   : integer range 0 to 1  := 0;
		variable read_head   : integer range 0 to 3  := 0;
		variable mux_flag    : integer range 0 to 1  := 0;;
	begin
	
	if rising_edge(clk) then
	
		--if(microseconds > 3000000) then
	
	case SPIState is
		
				when Init =>
					if(mux_flag = 0) then
						fifo_memory(0) := X"04";
						--fifo_memory(1) := X"03";
						mux_flag := 1;
						SPIState := D1;
					else
						fifo_memory(0) := X"34";
						--fifo_memory(1) := X"03";
						mux_flag := 0;
						SPIState := D1;
					end if;
				when D1 =>
					fifo_head := 0;
					cs_n <= '0';
					if(busy_transfer = '0') then
					   read_head := 0;
					   read_memory(read_head) := spi_rx_data;
						spi_tx_data <= fifo_memory(fifo_head);
						SPIState := T1;
					end if;
					
				when T1 =>
					trigger_transf <= '1';
					SPIState := B1;
					fifo_head := 1;
				
				when B1 =>
					if(busy_transfer = '1') then
						trigger_transf <= '0';
						SPIState := D2;
					end if;
					
				when D2 =>
					if(busy_transfer = '0') then
					   read_head := 1;
					   read_memory(read_head) := spi_rx_data;
						spi_tx_data <= fifo_memory(fifo_head);
						SPIState := T2;
					end if;
				
				when T2 =>
					trigger_transf <= '1';	
					SPIState := B2;
					
				when B2 =>
						if(busy_transfer = '1') then
							trigger_transf <= '0';
							SPIState := D3;
							--cs_n <= '1';
						end if;
					
				when D3 =>
					if(busy_transfer = '0') then
					   read_head := 2;
					   read_memory(read_head) := spi_rx_data;
						spi_tx_data <= x"00";
						SPIState := T3;
					end if;
					
				when T3 =>
					trigger_transf <= '1';
					SPIState := B3;
					
				when B3 =>
						if(busy_transfer = '1') then
							trigger_transf <= '0';
							SPIState := D4;
						end if;
						
				when D4 =>
					if(busy_transfer = '0') then
					   read_head := 3;
					   read_memory(read_head) := spi_rx_data;
						spi_tx_data <= x"00";
						SPIState := T4;
					end if;
					
			   when T4 =>
					trigger_transf <= '1';
					SPIState := B4;
					
				when B4 =>
					if(busy_transfer = '1') then
						trigger_transf <= '0';
						SPIState := Stop;
						--cs_n <= '1';
					end if;
				when Stop =>
					if(busy_transfer = '0') then
						cs_n <= '1';
						SPIState := Delay;
						
					end if;
				when Delay =>
					counter <= counter + 1;
					if(counter >= 3000000) then
						SPIState := Restart;
						counter <=  X"00000000";
						cs_n <= '0';
					end if;
				when Restart =>
					if(miso = '0') then
						SPIState := Init;
					end if;
					
		when others =>
			null;
			
	end case;
			
		--end if;
	
	end if;
	
	end process CONFIGURE_ADC;