New Contributor
Frequent Contributorsorry , got into other issue and couldnt able to reply timely ,
About the Signals and variables ,
There are lot of difference using signal and variables in RTL and one important difference is Variable assign the values immediately whereas signals depends on the logic use in the RTL (I.e mean combo or seq) . if Combo immdeiately assign it where as seq based on the logic it might take one /couple of clock cycles.
It is easy to understand if you create the test bench and see the RTL behavior in modelSIM.
About the timing , It looks really bad :(.Did you included the clock constraint ?
I am not sure what iam missing since both the CPLD from the same family and speed grade of the device are also same. here is what one more question Can you check the pin assignment since both are different package ? Also check the clock you connected to the global clock pins.
Thank you,
Regards,
Sree
