DE10-Nano mix GPIO I/O directions

Can you show your HDL code and/or schematic?

I'm not sure I understand your second question. Do you mean you need to instantiate a schematic design in your top-level HDL?

You can't use the same name for multiple top-level ports, as the error states. You could have something like GPIO_in and GPIO_out, each with the appropriate range, [15:0] and [19:0], respectively. The pinout of the device, configured in the Pin Planner, is where you'd differentiate between the upper 20 pins and the lower 16.

Same thing for your schematic. And there's nothing wrong with a top-level HDL file. But to add the schematics, you have to instantiate them in the HDL code like any other code instantiation:

<component name> #(<parameter mapping if any>) <instance name> (<port map>);

For example for a simple multiplier with a single parameter, give it a unique instance name, pass in the mult_size value to the width_in parameter, and map each signal in top-level HDL code with the port in the instantiated design:

multa #(.width_in(mult_size))

u1 (.in_a(dataa), .in_b(datab), .mult_out(mult_out));

The dot (.) ports are the ports of the lower-level design. The signal names in parentheses are the signals they connect to.

If you're not familiar with the basics of Verilog, this is a good place to start:

https://learning.intel.com/developer/learn/course/external/view/elearning/235/verilog-hdl-basics

As I said previously, you cannot mix inputs and outputs within the same bus name. You need to separate them out.

And "GPIO_1" is just the name of that jumper in the picture you attached from the DE10-Nano user guide. In other words, you can name the signals whatever you want in your code or schematic design, but they must have different names for input and output signals/busses. Again, you could simply use GPIO_in [15:0] and GPIO_out[19:0]. And then you assign those to the pin numbers shown in the picture to make the correct connections to the GPIO_1 jumper (JP7). Pin AG24, for example, does not need to be connected to a signal named "GPIO_1[16]". The picture is just showing you which physical jumper locations are connected to which I/O pins of the FPGA.

The "auto-assignments" you show in figure 2 do not look like Fitter assignments since I presume that is the All Pins list in the Pin Planner. Fitter assignments do not appear in the All Pins list. They only appear as green pins in the Pin Planner chip view when you select Show Fitter Placements from the View menu or toolbar. User (manual) assignments do appear in the All Pins list and appear as reddish-brown pins in the chip view of the Pin Planner.

Are you using a project template (.par) or something to set the I/O locations and/or pin names for this design? Your issues aren't making sense otherwise.

Hi Sstrell,

Thanks as always for weighing in.

A segment of the schematic is attached. This isn’t the final design, it’s a simple test to figure out if I know what I’m doing. As such, it’s been successful at demonstrating I don’t.

HDL is below. It codes what I’m trying to accomplish with a mix of GPIO_1 inputs and outputs and generates the following error: Error (10134): Verilog HDL Module Declaration error at FullRegister.v(26): port "GPIO" is declared more than once

I guess the fundamental question is: is HDL the right approach to declaring the top-level? If it is, how do I get the Fitter to assign my schematic inputs and outputs to the appropriate GPIO_1 pins?

As to my second question: I read that I should instantiate my schematics in the HDL. The schematic is RegU.bdf, ultimately, my design will have many .bdfs. So, the question is do I instantiate all in the HDL, and if so, how?

Thanks again,

Bill McDonald

module FullRegister(

//////////// CLOCK //////////

input FPGA_CLK1_50,

input FPGA_CLK2_50,

input FPGA_CLK3_50,

//////////// KEY //////////

input [1:0] KEY,

//////////// LED //////////

output [7:0] LED,

//////////// SW //////////

input [3:0] SW,

//////////// GPIO_1, GPIO connect to GPIO Default //////////

input [15:0] GPIO,

output [35:16] GPIO

);

//=======================================================

// REG/WIRE declarations

//=======================================================

//=======================================================

// Structural coding

//=======================================================

endmodule

Hi Sstrell,

I thought I’d successfully replied several days ago, but apparently it didn’t take. My responses embedded below in red.

Thanks,

Bill

You can't use the same name for multiple top-level ports, as the error states. Yes, completely understand. You could have something like GPIO_in and GPIO_out, each with the appropriate range, [15:0] and [19:0], respectively. This is where I’m having trouble. I tried very similar pin naming, but, because they’re not named exactly GPIO, Quartus assigns them other than GPIO Pins. I tried using Pin Planner to reassign them to GPIO Pins. But, because they’re reserved for GPIO I guess, I’m told they already in use. The pinout of the device, configured in the Pin Planner, is where you'd differentiate between the upper 20 pins and the lower 16. I suspect this is the answer, but I haven’t been able to figure out how to do. Would you please elaborate?

Same thing for your schematic. And there's nothing wrong with a top-level HDL file. But to add the schematics, you have to instantiate them in the HDL code like any other code instantiation:

<component name> #(<parameter mapping if any>) <instance name> (<port map>);

For example for a simple multiplier with a single parameter, give it a unique instance name, pass in the mult_size value to the width_in parameter, and map each signal in top-level HDL code with the port in the instantiated design:

multa #(.width_in(mult_size))

u1 (.in_a(dataa), .in_b(datab), .mult_out(mult_out));

The dot (.) ports are the ports of the lower-level design. The signal names in parentheses are the signals they connect to.

If you're not familiar with the basics of Verilog, this is a good place to start:

https://learning.intel.com/developer/learn/course/external/view/elearning/235/verilog-hdl-basics Thanks, I’ll definitely study. I’ve come to appreciate how powerful HDL is compared to conventional schematics. However, for this project, I need the schematic, visual presentation.

Hi Sstrell,

I think I'm getting it now. My mistake is in thinking Fitter or some other auto-mechanism would assign pins for me if I gave them "System Recognizable Names" in the schematic and/or the .v. I see now that this is not the case; I can name them whatever and then manually assign them in Pin Planner to connect them to GPIO_1, right?

Yes, it's All Pins List.

No, not using Project Template, just the .v, which is included in an earlier post above.

I'd really appreciate your confirmation that I now have this right or correction if I don't. Regardless, I plan to close the case after hearing from you and greatly appreciate you staying with me on it. Fact is, this was supposed to just be an easy test of some of my design approaches. The system I'm working toward will have much more than can be handled with the GPIOs and will require me to implement an I2C with Bus Expanders (MCP23017).

Thanks,

Bill