DE10-Nano mix GPIO I/O directions

Hi Sstrell,

Thanks as always for weighing in.

A segment of the schematic is attached. This isn’t the final design, it’s a simple test to figure out if I know what I’m doing. As such, it’s been successful at demonstrating I don’t.

HDL is below. It codes what I’m trying to accomplish with a mix of GPIO_1 inputs and outputs and generates the following error: Error (10134): Verilog HDL Module Declaration error at FullRegister.v(26): port "GPIO" is declared more than once

I guess the fundamental question is: is HDL the right approach to declaring the top-level? If it is, how do I get the Fitter to assign my schematic inputs and outputs to the appropriate GPIO_1 pins?

As to my second question: I read that I should instantiate my schematics in the HDL. The schematic is RegU.bdf, ultimately, my design will have many .bdfs. So, the question is do I instantiate all in the HDL, and if so, how?

Thanks again,

Bill McDonald

module FullRegister(

//////////// CLOCK //////////

input FPGA_CLK1_50,

input FPGA_CLK2_50,

input FPGA_CLK3_50,

//////////// KEY //////////

input [1:0] KEY,

//////////// LED //////////

output [7:0] LED,

//////////// SW //////////

input [3:0] SW,

//////////// GPIO_1, GPIO connect to GPIO Default //////////

input [15:0] GPIO,

output [35:16] GPIO

);

//=======================================================

// REG/WIRE declarations

//=======================================================

//=======================================================

// Structural coding

//=======================================================

endmodule