New ContributorHi:
During the test of the DDR4 controller, we found that the data write DQ signal was abnormal, but the timing of the data read was normal and the data read was correct. The cause of the abnormal data write DQ data signal has not been found so far, can anyone help analyze it?
thank you very much！
Frequent ContributorHi Sir,
It is very hard to analyze the analog data like this. Are you start seeing the IP give the cal fail results or bit errors?
New ContributorFor the current test, the interface timing calibration occasionally has a calibration failure, but recalibration after the failure can be passed. After the calibration is completed, the data read and write access test data can be transmitted normally, and there is no data error in the data verification. Only the oscilloscope observes the write timing is not normal
Frequent ContributorHi are you using Arria 10 device.
See if it is impact by this issue-> https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/fb292783.html
You may try the suggested workaround.
Frequent ContributorBy the way, when you measure the waveform, is it during calibration or read/write stage?
