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LLian22's avatar
LLian22
Icon for New Contributor rankNew Contributor
6 years ago

DDR4 interface signal test abnormal

Hi: During the test of the DDR4 controller, we found that the data write DQ signal was abnormal, but the timing of the data read was normal and the data read was correct. The cause of the abnormal d...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

It is very hard to analyze the analog data like this. Are you start seeing the IP give the cal fail results or bit errors?