DDR4 HILO in S10MX failed initialization

Hi,

Thank you for joining this Intel Community.

When you run project from Quartus 18.1, do you facing similar issue?

Can you please check on the PLL signal? I suspect the PLL loses lock and this will assert the reset signal until the PLL is locked. The reset signal need to de-assert in order for the controller being enable. Kindly, please check on this two signals.

At the meantime, I will recommend you go through the calibration checklist. See if there any item that list in calibration checklist is suspect as the failure’s root cause.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/calibration-checklist.html

Hope this helps. Let me know your feedback.

Thanks

Regards,

Aida

Also please allow me sometime to look into the design and see if I can duplicate the issue from my side. I'll keep ypu updated.

Thank you for your quick reply.

I also built the sample project in Quartus Pro 18.1 and got the same problem.

I'm not sure which PLL signal you mentioned as I didn't change anything in the sample project.

You can see the reset_n = 1 with local_reset_done = 1 in the SignalTap

Also, no timing violation was reported in TimeQuest.

Please let me know how I can fix it.

Thanks,

Hi Aida,

I wonder if you have time to look into the DDR4 HILO problem.

Thank you very much,