Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Creating a clock pulse

I am trying to create 7 different clock pulses that will go from high to low at a certain time. Can anyone help me?

This is what I have so far:

library IEEE;

use IEEE.std_logic_1164.all;

entity OpenValve is

port(

A,B,C,D,E,F,G: in bit;

H,I,J,K,L,M,N: out bit;

clockOut_1: out std_logic;

clockOut_2: out std_logic;

clockOut_3: out std_logic;

clockOut_4: out std_logic;

clockOut_5: out std_logic;

clockOut_6: out std_logic;

clockOut_7: out std_logic

);

end OpenValve;

architecture OPEN_VALVE_1 of OpenValve is

signal O: std_logic:='1';

signal P: std_logic:='1';

signal Q: std_logic:='1';

signal R: std_logic:='1';

signal S: std_logic:='1';

signal T: std_logic:='1';

signal U: std_logic:='1';

begin

H <= '1' when A='1' else '0';

I <= '1' when B='1' else '0';

J <= '1' when C='1' else '0';

K <= '1' when D='1' else '0';

L <= '1' when E='1' else '0';

M <= '1' when F='1' else '0';

N <= '1' when G='1' else '0';

process (O) is

begin

if(O='0') then

O<='1' after 5ns;

end if;

end process;

process (P) is

begin

if(P='0') then

P<='1' after 5ns;

end if;

end process;

process (Q) is

begin

if(Q='0') then

Q<='1' after 5ns;

end if;

end process;

process (R) is

begin

if(R='0') then

R<='1' after 5ns;

end if;

end process;

process (S) is

begin

if(S='0') then

S<='1' after 5ns;

end if;

end process;

process (T) is

begin

if(T='0') then

T<='1' after 5ns;

end if;

end process;

process (U) is

begin

if(U='0') then

U<='1' after 5ns;

end if;

end process;

clockOut_1<=O;

clockOut_2<=P;

clockOut_3<=Q;

clockOut_4<=R;

clockOut_5<=S;

clockOut_6<=T;

clockOut_7<=U;

END OPEN_VALVE_1;

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You know that the behavioural timing statements as wait for, after are for simulation only, not for synthesizable code (FPGA programs)?

    Your construct may not necessarily work in simulation, cause it misses a trigger event: 

    process (O) is
begin
if(O='0') then
O<='1' after 5ns;
end if;
end process;

    This is a usual form 

    process
begin
wait for 5 ns;
O<='1';
wait;
end process;

    To generate clock pulses in FPGA you need an input clock, and flipflops respectively a state machine to create a program flow.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Instead of initializing the signal O otherwise, the Initialization should be included with the process. Also the intermediate signals aren't needed: 

    process
begin
clockOut_1<='0';
wait for 5 ns;
clockOut_1<='1';
wait;
end process;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thank you for your help KVM. As for the other signals, we wanted to generate 7 output signals that will pulse from one to zero after the switch is triggered. These signals will then go to AND gates where the pulse will go through the circuit. Is this possible with this board?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I don't see a trigger in your example. As said, the after xx ns or wait for xx ns doesn't work in hardware synthesis.

    If you use a clock and register or counter to generate a delay, the input events are sampled to the clock, causing a delay jitter. So zhe clock frequency must be rather high for a precise short delay, e. g. a PLL multiplied frequency.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I meant, that I can't see that the pulse generation in your example depends on any input signal. So I don't know, what's exactly the purpose of your design, it seems incomplete.

    Do you intendend a fixed delay of 5 ns, or is the value only an example? As I said, a delay generation by a synchronous circuit with a clock would introduce a delay jitter. How much jitter is acceptable? A small delay as 5 ns may be easier achievable with delays through logic elements. The input/output delay of the FPGA would be already several ns.

    A variable, jitter-free short delay may be easier to achieve with a hardware one-shot. It's not a typical FPGA task.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The input signal will come from a keypad or other input device that we will attach to the microcontroller. From there, the switch will be turned on for a certain amount of time and then switched back to zero. These pulses will then go out of the microcontroller to AND gates to control Solid state relays which will then open voltage-controlled solenoid valves. Would this be possible to do with J-K flip flops or is there another way we can easily do this? Thank you again for all of your help.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    ... we wanted to generate 7 output signals that will pulse from one to zero after the switch is triggered. These signals will then go to AND gates where the pulse will go through the circuit.

    --- Quote End ---

    --- Quote Start ---

    These pulses will then go out of the microcontroller to AND gates to control Solid state relays which will then open voltage-controlled solenoid valves.

    --- Quote End ---

    Maybe in this application it won't hurt if there are glitches on these outputs, but be aware that combinational logic driving the signals directly can cause glitches. If these signals will be used internal to the FPGA to clock registers, then be especially careful. There is information about logic-driven clocks and in particular about the logic causing glitches on clocks at http://www.alteraforum.com/forum/showthread.php?t=2388.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I think we've decided to change our design to using a state machine which will include the and gates and make our design more compact. I appreciate your help man.