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Honored Contributor
Honored ContributorCreating a clock pulse
I am trying to create 7 different clock pulses that will go from high to low at a certain time. Can anyone help me? This is what I have so far: library IEEE; use IEEE.std_logic_1164.all; ...
Altera_ForumHonored Contributor
Honored ContributorI don't see a trigger in your example. As said, the after xx ns or wait for xx ns doesn't work in hardware synthesis.
If you use a clock and register or counter to generate a delay, the input events are sampled to the clock, causing a delay jitter. So zhe clock frequency must be rather high for a precise short delay, e. g. a PLL multiplied frequency.
