Creating a clock pulse

You know that the behavioural timing statements as wait for, after are for simulation only, not for synthesizable code (FPGA programs)?

Your construct may not necessarily work in simulation, cause it misses a trigger event:

process (O) is
begin
if(O='0') then
O<='1' after 5ns;
end if;
end process;

This is a usual form

process
begin
wait for 5 ns;
O<='1';
wait;
end process;

To generate clock pulses in FPGA you need an input clock, and flipflops respectively a state machine to create a program flow.