Creating a clock pulse

I meant, that I can't see that the pulse generation in your example depends on any input signal. So I don't know, what's exactly the purpose of your design, it seems incomplete.

Do you intendend a fixed delay of 5 ns, or is the value only an example? As I said, a delay generation by a synchronous circuit with a clock would introduce a delay jitter. How much jitter is acceptable? A small delay as 5 ns may be easier achievable with delays through logic elements. The input/output delay of the FPGA would be already several ns.

A variable, jitter-free short delay may be easier to achieve with a hardware one-shot. It's not a typical FPGA task.