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... we wanted to generate 7 output signals that will pulse from one to zero after the switch is triggered. These signals will then go to AND gates where the pulse will go through the circuit.
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These pulses will then go out of the microcontroller to AND gates to control Solid state relays which will then open voltage-controlled solenoid valves.
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Maybe in this application it won't hurt if there are glitches on these outputs, but be aware that combinational logic driving the signals directly can cause glitches. If these signals will be used internal to the FPGA to clock registers, then be especially careful. There is information about logic-driven clocks and in particular about the logic causing glitches on clocks at
http://www.alteraforum.com/forum/showthread.php?t=2388.
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