Communication PC-De0 Nano

Not yet. The last 2 or 3 days, I'm concentrating at my sensor. This afternoon, I'll try the virtual jtag.

Thank you so much Dave

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For your first design, you can ignore all of these signals, and just wire ir_in to your LEDs, and ir_out to some push buttons. You can then use quartus_stp and device_virtual_ir_shift to write to the LEDs and read from the push buttons.

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Hello Dave,

You said thqt ir_in is an input to my design and ir_out is the output from my design.

I don't understand. Why should ir_in connected to LED? Because my design is only to make 4 LED blinking by using 4 bit counter. And I use clock divider to slow the clock that will be fed to the counter. If ir_in is connected to LED, that means the virtual jtag will interfere the "original" design.

So far these are what I've done:

1. Make the original design with verilog and later generate a bdf(block diagram file)

2. Make the vji using megawizard. And only generate bdf file.

3. From this step on, I don't know what should I do. How should I connect the block of my design and virtual jtag block.

How could I know how much width of IR is needed?(page3 of virtual jtag megawizard)

What I know from the pdf you gave me, IR is to define to which data TDI and TDO should connect(though I don't understand that).

Why Altera don't give tutorial about this issue? They only discuss theory and how to use the megawizard not how to apply the megawizard to our design.

Sorry that I'm asking too much.

It's good to hear someone is trying to fill that gap.

Thank you Dave.

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You said thqt ir_in is an input to my design and ir_out is the output from my design. I don't understand. Why should ir_in connected to LED?

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You indicated you wanted to investigate the sld_virtual_jtag component. You can do that by simply instantiating it and wire it to the I/O on your board, eg. something like:

    -- Virtual JTAG interface
    u1: sld_virtual_jtag
        generic map (
            sld_auto_instance_index => "YES",
            sld_instance_index      => 0,
            sld_ir_width            => VIR_WIDTH,
            sld_sim_action          => "",
            sld_sim_n_scan          => 0,
            sld_sim_total_length    => 0,
            lpm_type                => "sld_virtual_jtag"
        )
        port map (
            -- JTAG signals
            tck                => tck,
            tms                => tms,
            tdo                => tdio,
            tdi                => tdio,
            -- Virtual instruction register
            ir_in              => vir_in,
            ir_out             => vir_out
      );
      led <= vir_in;

where VIR_WIDTH is the number of LEDs.

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Because my design is only to make 4 LED blinking by using 4 bit counter. And I use clock divider to slow the clock that will be fed to the counter. If ir_in is connected to LED, that means the virtual jtag will interfere the "original" design.

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That's a different design. In this design, if you want to use the JTAG interface to say load the initial count, or disable the counter, you have to ensure you cross clock domains from the JTAG interface clock to the 50MHz clock domain correctly.

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So far these are what I've done:

1. Make the original design with verilog and later generate a bdf(block diagram file)

2. Make the vji using megawizard. And only generate bdf file.

3. From this step on, I don't know what should I do. How should I connect the block of my design and virtual jtag block.

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Stop using BDF. Wire the parts up using Verilog. You will need to learn how to use the Modelsim simulator eventually, and its much easier if you stick with an HDL language.

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How could I know how much width of IR is needed?(page3 of virtual jtag megawizard)

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How do you know how wide a counter should be? Its just a port, you make it as wide as you decide you need it (within the limit of the IP; 24-bits I think for the IR width).

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What I know from the pdf you gave me, IR is to define to which data TDI and TDO should connect(though I don't understand that).

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IR is used as an 'instruction' register in the JTAG terminology. In this particular component, its just an output port. You can do with it what you like.

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Why Altera don't give tutorial about this issue? They only discuss theory and how to use the megawizard not how to apply the megawizard to our design.

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Yep, I understand your pain :)

Cheers,

Dave

Hello Dave,

I think I am really hopeless here with vji.

Have you already finished the tutorial already? Please finish it. I really need everyone's help.

I found an example about vji from pdf you gave. Here is the code:

module counter (clock, my_counter);

input clock;

output [3:0] my_counter;

reg [3:0] my_counter;

always @ (posedge clock)

if (load && e1dr) // decode logic: used to load the counter my_counter

my_counter <= tmp_reg;

else

my_counter <= my_counter + 1;

// Signals and registers declared for VJI instance

wire tck, tdi;

reg tdo;

wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;

wire [1:0] ir_in;

// Instantiation of VJI

my_vji VJI_INST(

.tdo (tdo),

.tck (tck),

.tdi (tdi),

.tms(),

.ir_in(ir_in),

.ir_out(),

.virtual_state_cdr (cdr),

.virtual_state_e1dr(e1dr),

.virtual_state_e2dr(e2dr),

.virtual_state_pdr (pdr),

.virtual_state_sdr (sdr),

.virtual_state_udr (udr),

.virtual_state_uir (uir),

.virtual_state_cir (cir)

);

// Declaration of data register

reg [3:0] tmp_reg;

// Decode Logic Block

// Making some decode logic from ir_in output port of VJI

wire load = ir_in[1] && ~ir_in[0];

// Bypass used to maintain the scan chain continuity for

// tdi and tdo ports

bypass_reg <= tdi;

// Data Register Block

always @ (posedge tck)

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

// tdo Logic Block

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0];

else

tdo <= bypass_reg;

endmodule

I have questions about this example.

1. From the pdf, I can read that tck is the clock used for shifting the data in and out on the TDI and TD0 pins. In the example above, what is actually "always @ (posedge tck)"? What I don't understand is how it become a "clock"? It doesn't even wired to the "input clock" of "module counter". Is it just "automatically has the same clock as De0 nano has?

2. What does the following code mean?

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

Why is "tmp_reg[3:1]" instead of "tmp_reg[3:0]"? What is the value of "tmp_reg[0]" then?

I know that sdr will become 1 when DR scan shift operation occurs or tdi is valid.

Load will be 1 if ir_in[1] = 1 and ir_in[0] = 0. (Please correct me if I'm wrong)

3. What happens here?

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0]

else

tdo <= bypass_reg;

I take it that "tmp_reg[0] or bypass_reg" are values that changing. But it doesn't seems that "tmp_reg[0]" get value from anywhere.

Thank You Dave.

Gunardi

PS. please finish your tutorial. I do need it. Thank you for your effort so far.

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always @ (posedge clock)

if (load && e1dr) // decode logic: used to load the counter my_counter

my_counter <= tmp_reg;

else

my_counter <= my_counter + 1;

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You cannot use control signals from the JTAG clock domain in your 'clock' clock domain without first ensuring they are synchronized. You are on the right track though.

Draw yourself a timing diagram with two clocks, one for JTAG TCK and the JTAG signals, and then another for your counter. If your counter clock is faster than the JTAG TCK, then 'load' and 'e1dr' last for many clocks. You need to use synchronization logic to take the pulse from the JTAG clock domain into the 'clock' clock domain.

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// Data Register Block

always @ (posedge tck)

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

// tdo Logic Block

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0];

else

tdo <= bypass_reg;

endmodule

what is actually "always @ (posedge tck)"? What I don't understand is how it become a "clock"? It doesn't even wired to the "input clock" of "module counter". Is it just "automatically has the same clock as De0 nano has?

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The statement is Verilog syntax for 'do this at every rising edge of TCK'. TCK is the JTAG clock it comes into the device on the JTAG pins. The clock comes from the USB-Blaster on your board.

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2. What does the following code mean?

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

Why is "tmp_reg[3:1]" instead of "tmp_reg[3:0]"? What is the value of "tmp_reg[0]" then?

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sdr = Shift-DR, this signal is high when the JTAG data register is getting shifted. Think of it as a shift-register enable signal. The tmp_reg signal is being assigned its previous value right-shifted by 1, with tdi replacing the top-bit ... and that is a shift-register.

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3. What happens here?

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0]

else

tdo <= bypass_reg;

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This is a Verilog combinatorial statement. It says, every time there is a change on tmp_reg[0] or bypass_reg, run this block of logic, and then it looks at the load signal ... so this is bogus Verilog. If it was supposed to be combinatorial, then it would have load in the sensitivity list, and if it was supposed to be registered, it would have a posedge statement in the sensitivity list.

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PS. please finish your tutorial. I do need it.

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Sorry, I have not had a chance to work on it. I'll try and find some time soon.

Cheers,

Dave

Thank you for your reply and effort so far for the tutorial, Dave.

Could you give me another good link or pdf regarding this issue? I believe you have much more resource than I do.:)

I have been trying to find any, but I couldn't find any(including Altera).

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Could you give me another good link or pdf regarding this issue? I believe you have much more resource than I do.:)

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Here's the incomplete tutorial;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/vjtag.pdf)

I'm also writing another on the Altera JTAG-to-Avalon bridges and how to use those. I've used the Virtual JTAG interface and created my own VHDL versions. Those will also get documented and links posted (when I get a chance).

Cheers,

Dave

Thank you for the tutorial, Dave.

I will read it immediately.

Ps. Please notify me everytime you update this pdf.

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The USB interface to the DE0-nano is a USB-Blaster.

You can communicate from the host via a couple of mechanisms;

1) SLD Virtual JTAG core, and quartus_stp Tcl procedures

2) JTAG-to-Avalon-MM master and SystemConsole

3) Direct access via FTDI drivers

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I'm also trying to communicate via my PC to the DE0-Nano via the current USB connection. I was aiming to do basically option# 3, but Terasic wouldn't provide me any schematics for how the FTDI chip is connected to the Cyclone IV.

I'm now looking into the JTAG options. I'm curious about how I actually assign the pins for working with the JTAG? I noticed when I create a JTAG interface using the Qsys w/ NIOS I never have to make any assignments in the Pin planner.

I've tried to generate a vJTAG using the megafunction wizard, and I can get to the point where my block is created (I'm using the schematic entry), but I have no idea how I assign the pins. The JTAG pins are not available in the Pin Planner...Are they automatically connected somehow?

(I'm still very new to this JTAG stuff so I might be completed confused about how to work with it :-)

Thanks!

Chris

Hi Chris,

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I'm also trying to communicate via my PC to the DE0-Nano via the current USB connection. I was aiming to do basically option# 3, but Terasic wouldn't provide me any schematics for how the FTDI chip is connected to the Cyclone IV.

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Look at the DE2 schematics. Basically the FTDI parallel interface is connected to a CPLD, and the CPLD is connected to the JTAG pins on the FPGA. The CPLD implements an FTDI FIFO to CPLD logic bridge, and the CPLD logic implements a byte-stream command parser. The UrJTAG project has the commands that the USB-Blaster uses, and the FTDI drivers can be used to send those commands. However, the connection to the logic internal to the FPGA still has to use the JTAG interface, i.e., you have to understand the Virtual JTAG component or the JTAG-to-Avalon-MM bridge.

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I'm now looking into the JTAG options. I'm curious about how I actually assign the pins for working with the JTAG? I noticed when I create a JTAG interface using the Qsys w/ NIOS I never have to make any assignments in the Pin planner.

I've tried to generate a vJTAG using the megafunction wizard, and I can get to the point where my block is created (I'm using the schematic entry), but I have no idea how I assign the pins. The JTAG pins are not available in the Pin Planner...Are they automatically connected somehow?

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The JTAG pins are automatically connected. Read the document I posted. The JTAG hub is a block of logic that Altera uses to share the JTAG pins. If you use the Virtual JTAG component and an SignalTap instance, they both use the JTAG pins, so the HUB is there to multiplex data between the logic.

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(I'm still very new to this JTAG stuff so I might be completed confused about how to work with it :-)

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No problem. Feel free to ask questions.

Cheers,

Dave