--- Quote Start ---
always @ (posedge clock)
if (load && e1dr) // decode logic: used to load the counter my_counter
my_counter <= tmp_reg;
else
my_counter <= my_counter + 1;
--- Quote End ---
You cannot use control signals from the JTAG clock domain in your 'clock' clock domain without first ensuring they are synchronized. You are on the right track though.
Draw yourself a timing diagram with two clocks, one for JTAG TCK and the JTAG signals, and then another for your counter. If your counter clock is faster than the JTAG TCK, then 'load' and 'e1dr' last for many clocks. You need to use synchronization logic to take the pulse from the JTAG clock domain into the 'clock' clock domain.
--- Quote Start ---
// Data Register Block
always @ (posedge tck)
if ( load && sdr )
tmp_reg <= {tdi, tmp_reg[3:1]};
// tdo Logic Block
always @ (tmp_reg[0] or bypass_reg)
if(load)
tdo <= tmp_reg[0];
else
tdo <= bypass_reg;
endmodule
what is actually "always @ (posedge tck)"? What I don't understand is how it become a "clock"? It doesn't even wired to the "input clock" of "module counter". Is it just "automatically has the same clock as De0 nano has?
--- Quote End ---
The statement is Verilog syntax for 'do this at every rising edge of TCK'. TCK is the JTAG clock it comes into the device on the JTAG pins. The clock comes from the USB-Blaster on your board.
--- Quote Start ---
2. What does the following code mean?
if ( load && sdr )
tmp_reg <= {tdi, tmp_reg[3:1]};
Why is "tmp_reg[3:1]" instead of "tmp_reg[3:0]"? What is the value of "tmp_reg[0]" then?
--- Quote End ---
sdr = Shift-DR, this signal is high when the JTAG data register is getting shifted. Think of it as a shift-register enable signal. The tmp_reg signal is being assigned its previous value right-shifted by 1, with tdi replacing the top-bit ... and that is a shift-register.
--- Quote Start ---
3. What happens here?
always @ (tmp_reg[0] or bypass_reg)
if(load)
tdo <= tmp_reg[0]
else
tdo <= bypass_reg;
--- Quote End ---
This is a Verilog combinatorial statement. It says, every time there is a change on tmp_reg[0] or bypass_reg, run this block of logic, and then it looks at the load signal ... so this is bogus Verilog. If it was supposed to be combinatorial, then it would have load in the sensitivity list, and if it was supposed to be registered, it would have a posedge statement in the sensitivity list.
--- Quote Start ---
PS. please finish your tutorial. I do need it.
--- Quote End ---
Sorry, I have not had a chance to work on it. I'll try and find some time soon.
Cheers,
Dave
Honored Contributor
